Low Power VLSI Design and Technology

The following sections are included:

• EDITORIAL

• CONTENTS

The paper is a survey of the current status of research and practices in various disciplines of low-power VLSI developments. After briefly discussing the rationale of the contemporary focus on low-power design, it presents the metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency. The requirements to be fulfilled by process technologies and device structures are reviewed as well as several promising circuit design styles and ad hoc design techniques. The impact of the design automation tools is analyzed with a special emphasis on physical design and logic synthesis. A review of various architectural trade-offs, including power management, parallelism and pipelining, synchronous versus asynchronous architectures and dataflow transformations are covered, followed by a brief discussion of the impact of the system definition, software and algorithms to the overall power efficiency. Emerging semiconductor technologies and device structures are discussed and the paper is concluded with the trends and research topics for the future.

As electronic systems grow in functional complexity, hence size, the design is often forced into a multi-chip solution. For such systems, the power dissipation due to the off-chip drivers (OCDs) and the off-chip interconnect capacitance can contribute to a significant portion of the overall system power. Often, however, this excessive power dissipation is unwarranted, since a smaller OCD can be used to drive the transmission line load, hence reducing the net capacitance being switched. The objective of this paper is to enable power dissipation trade-off decisions during the high-level phases of design and to minimize the power dissipation of OCDs and their associated interconnect. First, a termination metric is described that uses width optimization of RLC interconnects. Then, in terms of a proposed linear driver model, the low power design objective is posed as an integer programming problem and a branch and bound enumeration algorithm is presented. The driver and interconnect sizes are determined which will preserve signal quality, dispense with additional termination components, meet delay requirements, and minimize the overall power dissipation.

While most transient analysis techniques of interconnect networks ignore the nonlinearity of the driving gates, most CMOS driver models do not take into account the distributed loads. In this paper, we propose a new CMOS driver model which can handle distributed-lumped loads for transient analysis and power dissipation analysis. The output current of the CMOS driver is represented by a linear-quadratic-exponential piecewise model, taking into account the slope of the input signal, nonlinear effects of the driver and interconnect effects of the load. The CMOS transient leakage (short-circuit) current, thus short-circuit power dissipation, can be accurately evaluated. The model provides accuracy comparable to that of SPICE3e2 with one or two orders of magnitude less computing time.

In this paper we study the optimal design of drivers for high-performance VLSI systems. Specifically, we design a driver for a given interconnect such that the signal delay is minimal, or a driver such that the power dissipation and chip area are minimal for a specified delay. For a driver consisting of the cascaded inverters, we first show that the well known method using a fixed size-ratio e (= 2.73) between consecutive inverters does not give the optimal design due to the over-simplified circuit model used. Based on the transistor's nonlinear I-V characteristics, we derive an analytic relationship among the parameters of signal delay, power dissipation, driver size, and interconnection load. Using this relationship, we obtain the optimal design of drivers for high-speed low power ICs. When driving a heavy load, the newly designed drivers can reduce the delay by up to 15%, and the power dissipation and chip area by up to one order as compared to the best known designs. The developed optimal driver has a significant impact on the design of high-performance ICs, such as the high-speed bus in microprocessors, interconnect circuit in MCMs, minimal delay clock network, buffers for sending signals from chip to packaging pads, and low power circuits. The practical design examples are given in the paper.

In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.