III. Silicon and SiGe DevicesNo Access

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

Electrical & Computer Engineering Department, New Jersey Institute of Technology, University Heights, Newark, NJ 07102, USA

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D. MISRA

Electrical & Computer Engineering Department, New Jersey Institute of Technology, University Heights, Newark, NJ 07102, USA

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, and

N. RAHIM

Electrical & Computer Engineering Department, New Jersey Institute of Technology, University Heights, Newark, NJ 07102, USA

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https://doi.org/10.1142/S0129156407004345Cited by:0 (Source: Crossref)

Abstract

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi_xO_y (20% SiO₂ based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔV_T) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔV_T in our devices shows an excellent match with that of SiO₂ based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔV_T as they quickly reach saturation.

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NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

Abstract

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