A 0.5–6.5-GHz 3.9-dB NF 7.2-mW active down-conversion mixer in 65-nm CMOS
Abstract
In the paper, a broadband CMOS active down-conversion mixer is presented. Specifically, a noise-canceling transconductor is developed to reduce the noise figure of the mixer. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture not only saves power consumption of the circuit, but also reduces the undesirable parasitics. Moreover, two passive π-type networks are exploited to absorb internal parasitics of the circuit and guarantee broadband operation. Implemented in an advanced 65-nm CMOS process, post-simulations show that, driven by 0 dBm sinusoidal LO signal, the proposed mixer provides a maximal conversion gain of 15 dB and a NF of 3.9–4.9 dB across RF input frequency range of 0.5–6.5 GHz. The IIP3 and IP1dB of 3.1 and −6.9 dBm are obtained, respectively. The mixer core consumes 7.2 mW from a 1 V supply.
