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ON THE DESIGN OF EFFICIENT MODULAR ADDERS

HARIDIMOS T. VERGOS

Computer Engineering and Informatics Department, University of Patras, 26 500, Greece

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CONSTANTINOS EFSTATHIOU

Informatics Department, TEI of Athens, 12 210, Greece

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https://doi.org/10.1142/S0218126605002726Cited by:11 (Source: Crossref)

Abstract

Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.

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