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A FPGA-BASED RECONFIGURABLE PARALLEL ARCHITECTURE FOR HIGH-PERFORMANCE NUMERICAL COMPUTATION

Computer Engineering Department, Positivo University, R. Prof. Pedro V. P. de Souza, 5300, 81280-330 Curitiba (PR), Brazil

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HEITOR SILVÉRIO LOPES

Bioinformatics Laboratory, Federal University of Technology — Paraná, Av. 7 de setembro, 3165, 80230-901 Curitiba (PR), Brazil

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CARLOS R. ERIG LIMA

Bioinformatics Laboratory, Federal University of Technology — Paraná, Av. 7 de setembro, 3165, 80230-901 Curitiba (PR), Brazil

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, and

MAURÍCIO PERRETTO

Computer Engineering Department, Positivo University, R. Prof. Pedro V. P. de Souza, 5300, 81280-330 Curitiba (PR), Brazil

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https://doi.org/10.1142/S0218126611007645Cited by:2 (Source: Crossref)

Abstract

Many real-world engineering problems require high computational power, especially regarding the processing time. Current parallel processing techniques play an important role in reducing the processing time. Recently, reconfigurable computation has gained large attention thanks to its ability to combine hardware performance and software flexibility. Also, the availability of high-density Field Programmable Gate Array devices and corresponding development systems allowed the popularization of reconfigurable computation, encouraging the development of very complex, compact, and powerful systems for custom applications. This work presents an architecture for parallel reconfigurable computation based on the dataflow concept. This architecture allows reconfigurability of the system for many problems and, particularly, for numerical computation. Several experiments were done analyzing the scalability of the architecture, as well as comparing its performance with other approaches. Overall results are relevant and promising. The developed architecture has performance and scalability suited for engineering problems that demand intensive numerical computation.

This paper was recommended by Regional Editor Eby G. Friedman.

Keywords:

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