Research PapersNo Access

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits

Center for Intelligent Signal and Imaging Research (CISIR), Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, 32610 Bandar Seri Iskandar, Perak, Malaysia

E-mail Address: ateeqsshaheen@gmail.com

Search for more papers by this author

Fawnizu Azmadi Hussin

Center for Intelligent Signal and Imaging Research (CISIR), Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, 32610 Bandar Seri Iskandar, Perak, Malaysia

Search for more papers by this author

, and

Nor Hisham Hamid

Center for Intelligent Signal and Imaging Research (CISIR), Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, 32610 Bandar Seri Iskandar, Perak, Malaysia

Search for more papers by this author

https://doi.org/10.1142/S0218126617500219Cited by:0 (Source: Crossref)

Abstract

Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique.

This paper was recommended by Regional Editor Zoran Stamenkovic.

Keywords:

References

1. T. Iwagaki, S. Ohtake and H. Fujiwara, A design methodology to realize delay testable controllers using state transition information, Proc. 19th European Test Symp. (ETS), (2004), pp. 168–173. Google Scholar
2. A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuits (Springer, 1998), p. 14. Crossref, Google Scholar
3. G. L. Smith, Model for delay faults based upon paths, Int. Test Conf. (ITC) (1985), pp. 342–351. Google Scholar
4. J. Savir and S. Patil, Broad-side delay test, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13 (1994) 1057–1064. Crossref, Web of Science, Google Scholar
5. K.-T. Cheng, S. Devadas and K. Keutzer, Delay-fault test generation and synthesis for testability under a standard scan design methodology, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 12 (1993) 1217–1231. Crossref, Web of Science, Google Scholar
6. S. DasGupta, R. G. Walther, T. W. Williams and E. B. Eichelberger, An enhancement to LSSD and some applications of LSSD in reliability, availability, and serviceability, 25th Int. Symp. Fault-Tolerant Computing Highlights from Twenty-Five Years (1995), p. 289. Google Scholar
7. B. I. Dervisoglu and G. E. Stong, Design for testability using scanpath techniques for path-delay test and measurement, Proc. Int. Test Conf. (ITC) (1991), p. 365. Google Scholar
8. V. Chickermane, E. M. Rudnick, P. Banerjee and J. H. Patel, Nonscan design-for-testability techniques for sequential circuits, Proc. 30th Int. Design Automation Conference (DAC) (1993), pp. 236–241. Google Scholar
9. S. Dey and M. Potkonjak, Nonscan design-for-testability techniques using RT-level design information, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16 (1997) 1488–1506. Crossref, Web of Science, Google Scholar
10. M. Altaf-Ul-Amin, S. Ohtake and H. Fujiwara, Design for hierarchical two-pattern testability of data paths, IEICE Trans. Inform. Syst. 85 (2002) 975–984. Google Scholar
11. M. Altaf-ul-Amin, S. Ohtake and H. Fujiwara, Design for two-pattern testability of controller-data path circuits, IEICE Trans. Inform. Syst. 86 (2003) 1042–1050. Google Scholar
12. Y. Yoshikaw, S. Ohtake, I. Inoue and H. Fujiwara, Design for testability based on single-port-change delay testing for data paths, Proc. 14th Asian Test Symp. (ATS) (2005), pp. 254–259. Google Scholar
13. M. E. J. Obien, S. Ohtake and H. Fujiwara, Delay fault ATPG for f-scannable RTL circuits, Int. Symp. Communications and Information Technologies (2010), pp. 717–722. Google Scholar
14. M. E. J. Obien, S. Ohtake and H. Fujiwara, F-scan test generation model for delay fault testing at RTL using standard full scan ATPG, 16th European Test Symp. (ETS’11) (2011), pp. 203–203. Google Scholar
15. K. Ho Fai and N. Nicolici, Functional scan chain design at RTL for skewed-load delay fault testing, Proc. 7th Asian Test Symp. (ATS’04) (2004), pp. 454–459. Google Scholar
16. I. Ghosh, A. Raghunathan and N. K. Jha, A design for testability technique for RTL circuits using control/data flow extraction, Proc. Int. IEEE/ACM Conf. Computer-Aided Design (1997), pp. 329–336. Google Scholar
17. I. Ghosh, A. Raghunathan and N. K. Jha, Design for hierarchical testability of RTL circuits obtained by behavioral synthesis, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16 (1997) 1001–1014. Crossref, Web of Science, Google Scholar
18. H. Wada, T. Masuzawa, K. Saluja and H. Fujiwara, A DFT method for RTL data paths achieving 100% fault efficiency under hierarchical test environment, European Test Workshop (1999). Google Scholar
19. S. Ohtake, H. Wada, T. Masuzawa and H. Fujiwara, A non-scan DFT method at register-transfer level to achieve complete fault efficiency, Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC) (2000), pp. 599–604. Google Scholar
20. H. Wada, T. Masuzawa, K. K. Saluja and H. Fujiwara, Design for strong testability of RTL data paths to provide complete fault efficiency, Int. Conf. VLSI Design (2000), pp. 300–305. Google Scholar
21. H. Fujiwara, H. Iwata, T. Yoneda and C. Y. Ooi, A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27 (2008) 1535–1544. Crossref, Web of Science, Google Scholar
22. A.-U.-R. Shaheen, F. A. Hussin, N. H. Hamid and N. B. Z. Ali, Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram, 5th Int. Conf. Intelligent and Advanced Systems (ICIAS) (2014), pp. 1–5. Google Scholar
23. S.-J. Wang and T.-H. Yeh, High-level test synthesis with hierarchical test generation for delay-fault testability, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28 (2009) 1583–1596. Crossref, Web of Science, Google Scholar
24. V. Singh, I. Inoue, K. K. Saluja and H. Fujiwara, Instruction-based self-testing of delay faults in pipelined processors, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14 (2006) 1203–1215. Crossref, Web of Science, Google Scholar
25. Y. A. Yoshikawa, Binding algorithm in high-level synthesis for path delay testability, 18th Asia and South Pacific Design Automation Conf. (ASP-DAC) (2013), pp. 546–551. Google Scholar
26. T. H. Cormen, Introduction to Algorithms (MIT Press, 2009). Google Scholar
27. L. Lingappan, S. Ravi and N. K. Jha, Satisfiability-based test generation for nonseparable RTL controller-datapath circuits, IEEE Trans. Comput.-Aided Desi. Integr. Circuits Syst. 25 (2006) 544–557. Crossref, Web of Science, Google Scholar
28. L. Lingappan and N. K. Jha, Satisfiability-based automatic test program generation and design for testability for microprocessors, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15 (2007) 518–530. Crossref, Web of Science, Google Scholar
29. I. Ghosh and M. Fujita, Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams, IEEE Trans. Comput.-Aided Desi. Integr. Circuits Syst. 20 (2001) 402–415. Crossref, Web of Science, Google Scholar
30. Z. Navabi, VHDL: Analysis and Modeling of Digital Systems (McGraw-Hill, 1997). Google Scholar