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Architectural Optimizations for a High-Throughput Sorted QR Decomposition Circuit in MIMO Communication Systems

Wei-Yang Chen

National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Road, Da’an District, Taipei, Taiwan

E-mail Address: M10202135@mail.ntust.edu.tw

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and

Chung-An Shen

http://orcid.org/0000-0002-0628-5129

National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Road, Da’an District, Taipei, Taiwan

E-mail Address: cashen@mail.ntust.edu.tw

Corresponding author.

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https://doi.org/10.1142/S0218126618502201Cited by:2 (Source: Crossref)

Abstract

This paper presents the VLSI architecture of a low-latency and high-throughput sorted-QR decomposition (SQRD) engine for multiple-input multiple-output (MIMO) communication systems. In order to achieve a high processing throughput, the proposed design is architected based on a novel pipelined Givens rotation (GR) structure comprising of multi-dimension COordinate rotation DIgital computer (CORDIC) (MD-CORDIC) processing elements (PEs). Moreover, this design delivers the vector norm and conducts the sorting operation as a by-product of the vectoring operation on the execution flow of the CORDIC process. Therefore, excessive overheads for norm-calculation and sorting are excluded, and thus the latency is greatly reduced and throughput is enhanced. In addition, the proposed SQRD engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentation caused by the real-valued decomposition of the channel matrix. This design has been synthesized, placed and routed, and the post-layout estimation results have shown that the processing throughput of the proposed SQRD architecture achieves an approximately 2 $x$ improvement compared to the prior arts.

This paper was recommended by Regional Editor Tongquan Wei.

Keywords:

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