Research PaperNo Access

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

Chaudhry Indra Kumar

Department of Electrical Engineering, Delhi Technological University, Rohini, New Delhi 110042, Delhi NCT, India

https://doi.org/10.1142/S0218126622501250Cited by:0 (Source: Crossref)

Abstract

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by $\sim$ $\sim$ 80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160 $MeV \cdot {cm}^{2}$ $MeV \cdot {cm}^{2}$ /mg in 32-nm CMOS technology.

This paper was recommended by Regional Editor Zoran Stamenkovic.

Keywords:

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