Flash-algorithm for helix fit
Abstract
We present a novel helix fit, based on an analytical method, on par with FPGA implementations in terms of speed. High-luminosity experiments exhibit event pileup (200 at the upgraded LHC).1,2 To cope with the data load, the concept of Hardware Track Trigger (in the Event Filter pipeline) emerged. The specific solution3 at ATLAS deploys a Stratix-10 FPGA chip in conjunction with a pre-fitted track database. The throughput is approximately 1.5 M tracks/s. Comparatively we can fit 7.6 M tracks/s (without pattern recognition, no field non-uniformity) on Xeon-Icelake – which puts our solution in a competitive position vis-á-vis the dedicated hardware one when pattern recognition (say Hough transform for stiff tracks, equivalent to resolution relaxation in Ref. 3) is included.
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