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High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

Bhanupriya Bhargava

Electronics and Communication Engineering Department, Institute of Technology & Management University, Gwalior, India

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Pradeep Kumar Sharma

Electronics and Communication Engineering Department, Institute of Technology & Management University, Gwalior, India

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, and

Shyam Akashe

Electronics and Communication Engineering Department, Institute of Technology & Management University, Gwalior, India

Corresponding author.

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https://doi.org/10.1142/S0219581X14500033Cited by:0 (Source: Crossref)

Abstract

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

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