Topographic profiling and dimensional measurement of VLSI structure by scanning tunneling microscopy

A new method of surface profiling and dimensional measurement of submicron VLSI structure by scanning tunneling microscope (STM) has been successfully tested. Compared to the scanning electron microscope (SEM), the STM operates in air, provides three-dimensional imaging and yields better resolution; therefore, the STM has a greater potential than the SEM. The measurement error caused by the geometry of the probe, the only outstanding issue affecting STM accuracy, is explored in detail. An improved technique for etching sharp and slender STM probes has been developed, enabling the STM to be applied to high-density, high-rise microelectronic structure and thereby reducing the measurement error caused by the probe geometry. Probes with ideal tip geometry, tip angle less than 3° and radius of 0.03 µm within 1 µm from the tip, can be consistently produced and are believed to be the best state of the art from known reports. Furthermore, the method of side-wall profiling and true profile reconstruction are developed to avoid the probe geometrical effect, making it possible for the STM to obtain an accurate topographical profile without cleaving the sample and viewing it from the edge as needed by the SEM. Self-calibration of the probe geometry by the STM is used for further compensation of the measurement errors. The same techniques developed in this study can also be applied to the atomic force microscope (AFM), a derivative of the STM, for profiling and measuring nonconductive samples.