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DESIGN OPTIMIZATION, FABRICATION AND TESTING OF A CAPACITIVE SILICON ACCELEROMETER USING AN SOI APPROACH

    https://doi.org/10.1142/S1465876303001575Cited by:1 (Source: Crossref)

    In this paper the design, fabrication and testing of the capacitive micro accelerometer with Silicon On Insulator (SOI) approach is presented. The beam location with respect to a rectangular mass is optimized, using finite element analysis (FEM) to minimize cross axis sensitivity. It is demonstrated that a simple KOH etching with the addition of the tert-butanol can be easily adopted to fabricate the accelerometer structure without any convex undercutting effects. The devices are tested by electrostatic actuation.