No Access

A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

HAIDAR M. HARMANANI

Department of Computer Science and Mathematics, Lebanese American University, Byblos 1401 2010, Lebanon

Search for more papers by this author

and

HASSAN A. SALAMY

Department of Computer Science and Mathematics, Lebanese American University, Byblos 1401 2010, Lebanon

Search for more papers by this author

https://doi.org/10.1142/S1469026806002052Cited by:3 (Source: Crossref)

Abstract

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

This work was supported in part by a grant from the Lebanese National Council for Scientific Research (CNRS) and by the Lebanese American University.

Keywords:

Remember to check out the Most Cited Articles!
Check out these titles in artificial intelligence!

References

M. Bushnell and V. Agrawal , Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits ( Kluwer-Academic Publishers , 2000 ) . Google Scholar
K. Chakrabarty, IEEE Trans. Computer-Aided Des. 19(10), 1163 (2000), DOI: 10.1109/43.875306. Crossref, Google Scholar
K. Chakrabarty, Test scheduling for core-based systems, Proc. Int. Conf. Computer-Aided Des. (1999) pp. 391–394. Google Scholar
R. Chou, K. Saluja and V. Agrawal, IEEE Trans. VLSI 5(2), 175 (1997), DOI: 10.1109/92.585217. Crossref, Google Scholar
G. L. Craig, C. R. Kime and K. K. Saluja, IEEE Trans. Comput. 37(9), 1099 (1988), DOI: 10.1109/12.2260. Crossref, Google Scholar
M.-L. Flottes, J. Pouget and B. Rouzeyre, SoC Design Methodologies, eds. M. Robertet al. (2002) pp. 401–412. Crossref, Google Scholar
T. Gonzales and S. Sahni, J. ACM 23, 665 (1976). Crossref, Google Scholar
H. Harmanani and H. Salamy, J. Circuits Syst. Comput. 15(3), 331 (2006), DOI: 10.1142/S0218126606003106. Link, Google Scholar
Y. Huanget al., Resource allocation and test scheduling for concurrent test of core-based SoC design, Proc. ATS (2001) pp. 265–270. Google Scholar
V. Iyengar and K. Chakrabarty, IEEE Trans. Comput.-Aided Des. 21(9), 1088 (2002), DOI: 10.1109/TCAD.2002.801102. Crossref, Google Scholar
V. Iyengar, K. Chakrabarty and E. Marinissen, Test wrapper and test access mechanism co-optimization for system-on-a-chip, Proc. Int. Test Conf. (2001) pp. 1023–1032. Google Scholar
V. Iyengar, K. Chakrabarty and E. Marinissen, Efficient wrapper/tam co-optimization for large socs, Proc. Des. Automat. Test Eur. (DATE) (2002) pp. 491–498. Google Scholar
E. Larsson, A. Larsson and Z. Peng, Linkoping University SOC Test Site. http://www.ida.liu.se/labs/eslab/soctest/klas/ . Google Scholar
E. Larsson and Z. Peng, An integrated system-on-chip test framework, Proc. Des. Automat. Test Eur. (2001) pp. 138–144. Google Scholar
E. Larsson and Z. Peng, Test scheduling and scan-chain division under power constraint, Proc. Asian Test Symp. (2001) pp. 259–264. Google Scholar
E. Larsson and Z. Peng, A reconfigurable power-conscious core wrapper and its application to SOC test scheduling, Proc. Int. Test Conf. (2003) pp. 1135–1144. Google Scholar
E. Larsson, Z. Peng and G. Carlsson, The design and optimization of SOC test solutions, Proc. ICCAD (2001) pp. 523–530. Google Scholar
V. Muresanet al., A comparison of classical scheduling approaches in power-constrained block-test scheduling, Proc. Int. Test Conf. (2000) pp. 882–891. Google Scholar
J. Pouget, E. Larsson and Z. Peng, SOC test minimization under multiple constraints, Proc. Asian Test Symp. (2003) pp. 312–317. Google Scholar
C. Ravikumar , G. Chandra and A. Verma , Simultaneous module selection and scheduling for power constrained testing of core based systems , Proc. VLSI Design ( 2000 ) . Google Scholar
M. Vecchi, S. Kirkpatrick and C. Gelalt, Science 220(4598), 671 (1983). Google Scholar
C. Su and C. Wu, J. Electron. Testing: Theory Appl. 20, 45 (2004), DOI: 10.1023/B:JETT.0000009313.23362.fd. Crossref, Google Scholar
M. Sugihara, H. Date and H. Yasuura, A novel test methodology for core-based system LSIs and a testing time minimization problem, Proc. Int. Test Conf. (1998) pp. 465–472. Google Scholar
D. Zhao and S. Upadhyaya, Adaptive test scheduling in SoC's by dynamic partitioning, Proc. Int. Symp. Defect Fault Tolerance VLSI Syst. (2002) pp. 334–342. Google Scholar
D. Zhao and S. Upadhyaya, IEEE Trans. Instrum. Meas. 53(2), 318 (2004), DOI: 10.1109/TIM.2003.822712. Crossref, Google Scholar
D. Zhao and S. Upadhyaya, IEEE Trans. CAD 24(6), 956 (2005). Crossref, Google Scholar
Y. Zorian, A distributed BIST control scheme for complex VLSI devices, Proc. 11th IEEE VLSI Test Symp. (1993) pp. 4–9. Google Scholar