APPLICATIONS OF EVOLUTION ALGORITHMS TO THE SYNTHESIS OF SINGLE/DUAL-RAIL MIXED PTL/STATIC LOGIC FOR LOW-POWER APPLICATIONS

We present single-rail and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay and power in an experimental 0.1µm and 0.13µm CMOS technologies as well as a 0.13µm floating-body partially depleted silicon-on-insulator (PDSOI) process. Our experimental results demonstrate that both single-rail and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as SOI CMOS technologies.