ON THE OPTIMAL DRIVERS OF HIGH-SPEED LOW POWER ICs

In this paper we study the optimal design of drivers for high-performance VLSI systems. Specifically, we design a driver for a given interconnect such that the signal delay is minimal, or a driver such that the power dissipation and chip area are minimal for a specified delay. For a driver consisting of the cascaded inverters, we first show that the well known method using a fixed size-ratio e (= 2.73) between consecutive inverters does not give the optimal design due to the over-simplified circuit model used. Based on the transistor's nonlinear I-V characteristics, we derive an analytic relationship among the parameters of signal delay, power dissipation, driver size, and interconnection load. Using this relationship, we obtain the optimal design of drivers for high-speed low power ICs. When driving a heavy load, the newly designed drivers can reduce the delay by up to 15%, and the power dissipation and chip area by up to one order as compared to the best known designs. The developed optimal driver has a significant impact on the design of high-performance ICs, such as the high-speed bus in microprocessors, interconnect circuit in MCMs, minimal delay clock network, buffers for sending signals from chip to packaging pads, and low power circuits. The practical design examples are given in the paper.