HIGH-PERFORMANCE FPGA IMPLEMENTATION OF COMPACT SINGLE ROUND AES DESIGN

This paper presents high-performance and compact architecture for single round Advance Encryption Standard (AES) security algorithm using feedback mode. Two design based on stated architecture has been implemented on virtex-4 Field Programming Gate Array (FPGA) device. These two designs differ in method used for sub-bytes function implementation, in first design Look-Up Tables (LUTs) and in second design fully combinational gates using Composite Field Arithmetic (CFA) has been employed for sub-byte function implementation. Fair performance comparison of these two designs with each other and with other well known previous claims has also been presented. Finally, LUTs based and CFA based designs are achieved with encryption rate and number of Configurable logic blocks (CLBs) slices 1.0497 Gbps/2571 and 880.81 Mbps/1668 respectively. These results are among the fastest hardware implementations with better area utilization.