A 0.975 $\mu$W 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference $V_{\mathrm{\text{cm}}}$ for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 $\mu \mathrm{\text{W}}$, resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.