Research PaperNo Access

Department of Electronics and Communication Engineering, National Institute of Technology, Arunachal Pradesh, Jote, India

and

Abir J. Mondal

https://orcid.org/0000-0001-8023-4103

Department of Electronics and Communication Engineering, National Institute of Technology, Arunachal Pradesh, Jote, India

E-mail Address: abir_jm@hotmail.com

Corresponding author.

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https://doi.org/10.1142/S0218126625500513Cited by:0 (Source: Crossref)

Abstract

This work presents an all-digital time-mode subthreshold temperature sensor for monitoring SoC self-heating problem. The sensor incorporated a low-power differential inverter interlaced cascaded delay cell followed by a gated ring oscillator with different temperature coefficients of $-$ $-$ 1736.10 and $-$ $-$ 5880.33 ppm/^∘C, respectively. The differential inverter interlaced cascaded delay cell and XOR gate produce a temperature-dependent large delay pulse, whereas the gated ring oscillator produces temperature-dependent output code for each point of temperature within the delay pulse generated by the differential inverter interlaced cascaded delay cell and XOR. The corresponding temperature code is recorded by an asynchronous counter. At 90-nm CMOS process and 0.6/0.3V supply voltage Vdd, the sensor occupies 0.009mm² and consumes only 876nW at 27^∘C. The sensor has a sampling rate of 52.16KS/s and the resolution is noted to be 0.40^∘C for a temperature span of 0–100^∘C. Besides, the proposed design achieves a very small energy/conversion of 17 pJ, which ensures 2.72 pJ $\times$ $\times$ C² and 0.13 nJ%² resolution FoM and inaccuracy FoM, respectively.

This paper was recommended by Regional Editor Giuseppe Ferri.

Keywords:

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