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FPGA technology, applied to the case of electronic system, needs to make full use of hardware resources, to achieve great efficiency and yield the largest returns. To apply digital chaotic sequence which consume least resource in encryption system, this paper seeks a tradeoff between logistic and skew tent discrete map aiming at hardware utilization through the method of testing critical precision. Critical precision (or delay) is firstly proposed to weigh the effect of different precision (or delay) on chaotic system according to the autocorrelation property of output sequences. In tests, a controlled variable approach is adopted. Firstly, build graphical module on DSP builder platform in Simulink library, and then transform that into VHDL hardware language running in Quartus II, in which way, considerable time is saved. The results show that: in respective critical precision, the logistic map allows higher hardware utilization and is suitable to lower resource implementation. Meanwhile, compared with skew tent map in the same precision, the autocorrelation, run and balance properties of logistic map are all more superior. Therefore, a logistic map is selected as a key generator in hardware cryptographic system.

SCA is one of the biggest threats to the security of encryption chip. It can crack the unprotected encryption chip at lower cost and faster speed, which weakens the security of the SM4 encryption algorithm circuit without any protection. In this paper, the SM4 encryption algorithm is implemented on FPGA. The pseudo-random sequence generated by discrete chaotic system is used to randomly mask the intermediate value in the SM4 encryption process. This will disrupt the power consumption in the encryption process, thus preventing power analysis. Experimental results show that the proposed chaotic mask scheme can effectively prevent intermediate value leakage and protect the SM4 encryption system from power analysis attack.