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There has been a growing interest from academia and industry in developing circuits and systems for edge computing and quality control tasks in food production lines, where image-processing is frequently required. This paper outlines the required considerations for designing a fruit classification system based on image-processing using Cellular Automata (CA) models and integrating it into reconfigurable hardware (HW) such as Field Programmable Gate Arrays (FPGAs). Parallel processing in CA requires numerous processing elements to be implemented and mapping CA models to HW generally comes with limitations. Homogeneous CA arrays are easier to design and implement in HW but can be resource-demanding. To fill this gap, this study explores different alternatives for the HW implementation of CA models, particularly trading computational-parallelism for a more optimized use of the available HW resources. We conducted experimental tests of the designed HW system using the Digilent Nexys development board, and the operation was validated against software-based benchmarks for image-processing, particularly concerning edge-detection. The presented study provides a broader range of design solutions for the HW implementation of two-dimensional CA models and a better understanding of their advantages and disadvantages. The results show that solutions focusing on instruction-parallelism add some complexity to the conception and require more design effort, compared to homogeneous CA models composed of identical cells. However, the instruction-parallel design solutions can significantly improve the HW resource utilization, especially when implementing computationally intensive CA rules in FPGAs.

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Blind source separation (BSS) is the process of extracting sources from mixed data without or with limited awareness of the sources. This paper uses field programmable gate array (FPGA) to create an effective version of the Blind source separation algorithm (ICA) with a single Multiply Accumulate (MAC) adaptive filter and to optimize it. Recently, space research has paid a lot of attention to this technique. We address this problem in two sections. The first approach is ICA, which seeks a linear revolution that can enhance the mutual independence of the mixture to distinguish the source signals from mixed signals. The second is a powerful flexible finite impulse response (FIR) filter construction that makes use of a MAC core and is adaptable. The adjustable coefficient filters have been used in the proposed study to determine the undiscovered system utilizing an optimal least mean square (LMS) technique. The filter tap under consideration in this paper includes 32 taps, and hardware description language (HDL) and FPGA devices were used to carry out the analysis and synthesis of it. When compared to the described architecture, the executed filter architecture uses 80% fewer resources and increases clock frequency by nearly five times, and speed is increased up to 32%.

An innovative reconfiguration application is proposed to re-calculate the parameters of the Ferragina and Manzini exact search algorithm (or FM indexes), using a modular and efficient hardware implementation to accelerate alignment programs of short DNA sequence reads. Although these programs use multi-core execution strategies or multiple computers, they have become slow considering the very high speed at which the new massively parallel sequencing machines produce the reads to be aligned. Consequently, a search for different ways to accelerate the alignment is crucial. The proposed design runs with software functions in a hybrid system, and has the ability to align millions of reads to reference as large as the human genome. Tests on the M505k325t card show that a single alignment core can accelerate the computation by a factor close to $10.64\times$ in relation to BWA. Due to the minor consumption of area and power, multiple alignment cores can fill the Field Programmable Gate Array (FPGA) by multiplying the computation speed. With a multiple-core implementation, the processing speed of the design outperforms applications that are accelerated by GPUs and competes with similar FPGA proposals whose cost is much higher.

Contemporary wideband radio telescope backends are generally developed on Field Programmable Gate Arrays (FPGA) or hybrid (FPGA+GPU) platforms. One of the challenges faced while developing such instruments is the functional verification of the signal processing backend at various stages of development. In the case of an interferometer or pulsar backend, the typical requirement is for one independent noise source per input, with provision for a common, correlated signal component across all the inputs, with controllable level of correlation. This paper describes the design of a FPGA-based variable correlation Digital Noise Source (DNS), and its applications to built-in testing and debugging of correlators and beamformers. This DNS uses the Central Limit Theorem-based approach for generation of Gaussian noise, and the architecture is optimized for resource requirements and ease of integration with existing signal processing blocks on FPGA.

With the ever-increasing data rates in radio astronomy, a universal Field Programmable Gate Array (FPGA)-based hardware platform which can be used at different locations in the signal processing chain, like a beamformer, data router or correlator, would reduce development time significantly. In this paper, we present the design of such a platform, the UniBoard². With UniBoard², both large rack-based and single-board systems can be made. Standard Quad Small Form-factor Pluggable (QSFP) input and output (IO) interfaces on the front side make it easy to interface UniBoard² to standard 40 Gigabit Ethernet (GbE) network equipment. Hardware design challenges, like transceiver links, power supplies, power dissipation and cooling are described. The paper concludes with some examples of systems (like beamformers and correlators) that can be built using the UniBoard² hardware platform.

One of the main technologies to open up a wider field of view for today’s radio telescopes are phased arrays. This is especially the case for radio astronomy instruments operating below 2GHz. Nowadays, the existing dish-type instruments are being upgraded with phased array feeds (PAF) in the focal plane. This increases the field of view at the expense of needing more analog electronics and digital signal processing. One of the digital signal processing functionalities used to combine the digitized signals from the PAF is a beam-former which creates multiple high sensitivity beams within the field of view of the dish. Before beams can be formed, the signals from the PAF need to be calibrated using a correlator. In this paper, we present a solution where these two operations are combined by using the beam-former also as a correlator. The statistics unit used as part of the beam-former implementation, can be used as well for calculating correlation products. With the proper settings of the beam-former weight of each beamlet, a frequency sub-band with a direction, can be used as a single cross correlation product. By implementing the correlator on the beam-former, the digital resources and development time can be reduced. To validate the idea, two versions of the algorithm are implemented in the Apertif PAF system on the Westerbork Synthesis Radio Telescope (WSRT). Results show that two full-bandwidth correlation matrices per beam, needed to determine the static beam weights for the calibration, and a single column of the correlation matrix, used to compensate for any drift between the receiver chains, can be performed.

The Square Kilometer Array Reconfigurable Application Board (SKARAB) is a Xilinx Virtex-7 FPGA-based platform designed for the MeerKAT array, to be used for both F- and X/B-engines. The MeerKAT F-engine receives digitized data, thus no samplers are required on the SKARAB-based platform. Among the alternative options available, a high-performing ADC mezzanine board can be used in conjunction with the SKARAB, which allows four 1.4-GHz-wide input channels to be digitized and processed. In this paper, we outline how the SKARAB has been successfully used for single-dish applications including imaging, spectroscopy, and spectro-polarimetry.