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This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves $66\%$ reduction on the average number of activated comparators compared to a conventional flash ADC.

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.