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DC offset and high flicker noise are the main problems for the direct conversion CMOS mixer design. A novel even harmonic switching mixer implemented in a standard 0.18 μm CMOS process for applications in 2.45 GHz direct conversion receivers is proposed. The mixer circuit overcomes the problems of DC offset and high flicker noise. It achieves -8.24 dB gain, 5.2 dB DSB noise figure at 100 KHz, 17.25 dBm IIP3 and zero DC power consumption.

In this paper, a novel circuit method is proposed to reduce 1/f³ (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/f³ output phase noise is reduced by 5.7dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18$\mu$m CMOS technology with 1.8V supply and 3.6mW power consumption. Post-layout simulations predict a phase noise of $-104$dBc/Hz for the proposed oscillator at 100KHz offset from 3.1GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6dBc/Hz at 100KHz and 1MHz offsets, respectively.

A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256kHz and 312.5Hz input with a differential-mode voltage of 700mV sinusoidal waveform. Based on SMIC 180nm/1.8V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52dB SNDR, 18.90-bit ENOB, and 8.40mW power consumption, which correspond to FoM${}_{\mathrm{\text{W}}}$ and FoM${}_{\mathrm{\text{schreier}}}$ of 0.067pJ/step and 163.27dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.