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This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.

The In:Ce:Cu:LiNbO₃ crystals used in this work were grown by Czchralski method. The key parameters: the exponential gain coefficient Γ, the diffraction efficiency η_S, the response time τ_w, the dynamic range M/#, the sensitivity S and the maximal refractive index change Δn_max were measured with conventional two beam coupling. The optimal values of Γ, η_S, M/#, S and Δn_max achieved are 44.7, 68.6%, 6.02, 0.471 cm/J and 5.37 × 10^-5, respectively. It was found that the blue light photorefractive properties of Γ, η_S, M/#, S and Δn_max increased with increasing In³⁺ ions concentration, while the red light photorefractive properties of Γ, η_S, Δn_max decreased with increasing In³⁺ ions concentration. The nonvolatile holographic storage properties were measured by both the dual wavelength and two color techniques. The maximal diffraction efficiency and fixing diffraction efficiency using the dual wavelength technique were doubled compared to those obtained in using the two color technique. The sensitivity and nonvolatile sensitivity were one order of magnitude higher than those by the two color technique. The photorefractive property enhancement by the dual wavelength technique was investigated.

In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.

The bio-mimetic structure of a neuron is taken into account for utilizing the electrophysiological data. These neuron circuits are entertained for the use in digital computers. At the end of Moore’s law, conventional technology is striking different difficulties, such as power consumption, area utilization, and energy efficiency. To conquer these hurdles, a nanoscale, the nonvolatile memristor used in the proposed neuron modified from the refined AH neuron. Synapses are also built using anti-parallel memristors. These neurons and synapse are joined together such that the performance metrics are analyzed the energy consumption is reduced by 89.656%. Besides, power consumption is limited by 37.568% and the spike frequency is measured as 10.263kHz when compared with the traditional CMOS synapse connected with the proposed neuron. Moreover, the measured energy per spike is 3.37fJ. The implementation of the neuron network is done by 45nm technology.

High performance computing system design based on complementary metal oxide semiconductor (CMOS) is facing more and more challenges due to the volatility, increased leak current and interconnection delay. Computations utilizing magnetic logic devices have attracted considerable interest as the potential alternatives because of their features of nonvolatility, re-configurability, unlimited endurance and low power consumption. Instead of using electron charges, the magnetic logic device stores and processes the data information by controlling spins, i.e., the magnetization states in a device. The emerging technologies related to the magnetic logic are mainly composed of three design schemes, i.e., the magnetoresistive logic, the magnetic quantum cellular automata and the magnetic domain wall logic. This paper will illustrate the principles as well as review the recent developments of these magnetic logic devices. Challenges and prospects of the future development are also discussed.

This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.