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Fluid scheduling allows tasks to be allocated with fractional processing capacity, which significantly improves the schedulability performance. For dual-criticality systems (DCS), dual-rate fluid-based scheduling has been widely studied, e.g., the state-of-the-art approaches mixed-criticality fluid scheduling (MCF) and MC-Sort. However, most of the existing works on DCS either only focus on the schedulability analysis or minimize the energy consumption treating leakage power as a constant. To this end, this paper considers the effect of temperature on leakage power and proposes a thermal and power aware fluid scheduling strategy, referred to as thermal and energy aware (TA)-MCF which minimizes both the energy consumption and temperature, while ensuring a comparable schedulability ratio compared with the MCF and MC-Sort. Extensive experiments validate the efficiency of TA-MCF.

Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuristic algorithm named nondominated sorting genetic algorithm-II (NSGA-II) has been employed for selecting suitable input polarity of mixed polarity dual Reed–Muller (MPDRM) expansion function to reduce the power-density. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Without performance degradation, the proposed MPDRM approach shows more than 50% improvement in the area and power savings and around 6% peak temperature reduction for the MCNC benchmark circuits than that of earlier literature at the logic level. Algorithmic optimized circuit decompositions are implemented in physical design domain using CADENCE INNOVUS and HotSpot tool and silicon area, power consumption and absolute temperature are reported to validate the proposed technique.

Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.