Narrow Results

The executions of various complex models reliant on quantum-dot cell automata (QCA) are of high eagerness for investigators. So far, the structure of complex adders in QCA is focused on bringing down clock delay, cell count, and logic gates. This paper proposes the circuit format of a 4-bit multiplier utilizing a carry save adder (CSA) and its implementation on QCA. The CSA is framed with another QCA design of the full adder circuit. The CSA gives preferable expansion strategies over Brent–Kung (BK) adder and Landler–Fisher (LF) adder. This multiplier represents fewer cell counts and clock delays conversely with past designs.

This study demonstrates the development of an innovative $n$-bit less power ripple carry incrementer (RCI) and decrementer (RCD) circuit, respectively, devised using quantum dot cellular automata (QCA). In order to increment or decrement two numbers, RCI and RCD are essential. With a revised configuration of the AND gate, half adder, and XOR gate circuit, the suggested ripple carry incrementer and decrementer circuits are realized. Modern designs for the XOR and half adder are contrasted with these freshly created ones. Circuits are designed using QCA designer 2.0.3. The 4-bit RCI, 8-bit RCI, and 16-bit RCI as well as 4-bit RCD, 8-bit RCD, and 16-bit RCD simulation results are compared to the theoretical findings.