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Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, …). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I/O scenarios where the peripherals operate. This software has been used to analyze the performance of four different processors in four I/O scenarios: video capture, video capture and playback, high speed network, and serial transmission.

A method to reduce the side effects of dual-line timed address-event (TAE) vision system is proposed in this paper. The side effects include edge discontinuity and the natural insensitivity to object edges in the motion direction. X-event, a kind of artificial event is introduced to represent light intensity difference perpendicular to the motion direction of the target object. New timestamps are attached to the raw TAE data to adjust temporary resolution to the same order of magnitude with the vertical axis in the TAE representation. After removing noisy and redundant events, designed templates are used to generate X-events to renovate broken lines and reproduce perpendicular edges. It is a real-time process which is unnecessary to wait for the collection of all the raw TAE data. A behavioral model of a 2 × 256 TAE vision sensor is established in Matlab, and X-events Generation block is realized in FPGA. Experimental results show that the proposed method can patch the TAE representation effectively to obtain a one-pixel-wide, precise, closed and connected contour.

We present the design and evaluation of a high-performance network-on-chip (NoC) focused on telecommunication and multimedia applications that tolerate latency and bandwidth variations. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel. Each flit carries routing information that is used by routers to perform arbitration and scheduling of the corresponding output ports in order to balance channel utilization. In order to compare our approach with others, we introduce an analytic model for the worst-case latency (WCL) of our NoC and recall those of related approaches. Analytic comparisons and experimental data show that our approach keeps average WCL lower for variable-bit-rate multimedia applications than a network based on resource reservation. For these applications, the overall throughput is larger than that of networks that perform resource reservation. A case study based on the proposed NoC shows that the average latency was 28% lower than the WCL expected for the experiment. Indeed, hard real-time flows designed considering the absolute WCL of the network will always meet the requirements of the associated hard real-time tasks, so no deadline can be lost due to network contention.

Eliminating the Gibbs oscillations that occur during the Finite Impulse Response (FIR) digital filter design with the Fourier Series method will ensure correct filtering. For this reason, the development of the window improves the performance of the filter and, therefore, the system. In this study, the cosh window function is designed using Particle Swarm Optimization, which is a preferred optimization method in many areas. Thus, alternatives to the standard results obtained from the existing traditional calculations will be produced, and different windows that perform the same function will be obtained. In addition, exponential and cosh window functions were designed in LabVIEW environment, which is a graphical programming language-based program, and the designed windows were analyzed at different parameter values. LabVIEW provides a fast and easy programming environment, and it provides the opportunity to realize real-time applications with its external hardware. Utilizing this feature, the amplitude spectrum of cosh window designed in LabVIEW is displayed in real time for different window parameter values. As a result, FIR digital filters were designed using cosh window based on optimization and the cosh window designed in LabVIEW, and the distorted EEG signal was filtered using these filters and displayed in real time.

The proposed system provides an energy management method for various types of an energy storage system including cascade utilization battery. The method is used to receive, store and manage the relevant operating data from the energy storage battery and also randomly determine the energy distribution coefficient of the energy storage battery. According to the adaptive energy distribution method, the power value of the total distributed energy storage power to the cascade utilization energy is calculated and also the energy distribution coefficient of the energy storage battery in real time is adjusted. Finally, the corrected command value of the energy storage battery power is obtained as an output. The system can not only prevent overcharging and over-discharging of the energy storage system, but also maintain the good performance of the energy storage system. To realize the coordinated control and energy management of the battery power plant, we use multiple types, including conventional battery and cascade utilization power battery control purpose. The performance metrics, namely, real-time energy management, computational time and operating cost are employed for the experimental purpose. The simulation results show the superior performance of the proposed energy management system over other state-of-the-art methods.