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This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except $X_i\cdot Y_i$ and $X_i\cdot Z_i)$ operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.

In this work, we present a new chaos-based cryptosystem scheme consisting of a noniterative plaintext transformation and a high dimensionally (K-map) populated dynamic Look-Up Table (LUT) with random access that outperforms the security and speed of previous LUT-based chaotic encryption schemes. Experimental analysis of the proposed scheme reveals excellent statistical properties, naturally extended permanent cycle, and high performance for real-time multimedia communications. Our scheme is one order of magnitude faster than the fastest LUT-based approach in the literature and robust to differential and chosen plaintext attacks.

The dynamical degradation of digital chaos brings serious defects to chaos-based digital systems and greatly restricts its applications. In this paper, we first discuss the integer logistic map (ILM) and calculate its cycle lengths under different precision. Then, a novel scrambling method based on coupling mode switching (CMS) strategy named CMSSM is proposed to enhance the chaotic features of digital chaos. Following the selection principles, we use three coupling mode candidates to construct 3CMSSM. Theoretical analysis shows that the output cycle length of 3CMSSM is three times that of scrambling methods used in single coupling mode (SCM) strategy. Numerical simulations are carried out to demonstrate the desirable statistical and dynamical properties of scrambled ILM. Finally, we design a (pseudo-random number generator) PRNG based on 3CMSSM. Both results of statistical test suites NIST SP800-22 and TestU01 show that the suggested PRNG has highly credible randomness compared to other algorithms.