International Journal of High Speed Electronics and Systems

In this work, we review the physical properties of organic materials and transistors, discussing especially the charge transport mechanisms. Finally, we present an analytical and continuous charge model for Organic Thin Film Transistors (OTFTs) from which analytical expressions of all the total capacitances are obtained. They are developed and finally written as continuous explicit functions of the applied voltage, resulting in a complete charge-based small-signal model composed by a unified charge control model derived from Poisson equation assuming an exponential density of localized states. This charge model was developed from a previously proposed analytical DC current model assuming a hopping based transport. Therefore our complete small signal model has the potential to be successfully used in circuit simulators for the design of OTFTs.

Au/P3HT (poly [3-hexylthiophene])/n-type crystalline silicon (n-c-Si) solar cells have been fabricated. The Aluminum back contact is obtained by evaporation on silicon substrate. An 80 nm P3HT layer thick was spin-coated on silicon substrate followed by thermal annealing. Finally golden contacts are deposited by sputtering. The best characteristics of this flawed solar cell are: V_oc=0.47 V, I_sc=7.42 mA/cm² and an efficiency of 1.29%. The area of this device is 0.07 cm². In order to get a deep understanding of the electrical properties of the heterojunction, capacitance-voltage and current-voltage-temperature measurements have been made. A compact electrical equivalent circuit has been used to describe the dark current-voltage characteristics. It is based on the combination of two exponential mechanisms, shunt and series resistances and space-charge limited current terms. From the temperature dependence of the extracted parameters we can obtain the limiting conduction mechanism. We found that the polymeric layer limits the current not only at low voltages, through Multi-Tunneling Capture Emission, but also at high voltages, through series resistance and Space-Charge Limited Current. On the other hand, the Silicon wafer limits the current at medium voltages, through the diffusion mechanism. In addition, the model is useful to estimate the open circuit voltage and built in voltage of the solar cell using only dark current voltage measurements.

The development of high performance thin-film transistors on flexible plastic substrates is of great importance for the manufacturing and industrialization of flexible electronic devices, such as flexible displays. Here we present different approaches to fabricate bottom-gate field-effect transistors on 25 μm heat stabilized polyethylene naphthalate (PEN) foil using photolithography and solution processing. The flexibility and dimensional instability of the substrate constituted the main challenge during manufacturing. We developed a novel method to handle the foils during processing by reversibly attaching them onto 6 inch Si wafers. The so-called foil-on-carrier assembly showed excellent flatness (about 1 μm) and good dimensional stability and tolerance towards the different processing steps up to 160°C. Transistors were made either using an organic polymer or an inorganic oxide as gate dielectric material. Source and drain gold electrodes were patterned using standard photoresist patterning followed by wet etching, or by lift-off. The feature sizes in the transistors were downsized from 5 μm to sub-micrometer to improve the performance. In order to achieve structures with high resolution, all functional layers were patterned using a commercial wafer stepper (PAS5500/100D). The two dielectric materials used and the two ways of making the source-drain resulted in four different metal-insulator-metal (MIM) stacks. The MIM stacks were characterized by optical microscopy, scanning electron microscopy and four point resistance measurements. Registration accuracies below 0.5 μm were found over the whole wafer. Transistor fabrication was finished by depositing pentacene derivatives from solution.

We describe the fabrication and characterization of organic photodiodes on solution cast ITO (tin doped indium oxide) bottom electrodes. ITO coatings were produced by gravure printing process on PET and PEN substrates. The sheet resistance could be decreased by heat treatment at 120°C under forming gas atmosphere (N₂/H₂) to 1.5 kΩ. The transmission of the ITO coated PET and PEN substrates is more than 80% in the visible range. The printed films were hardened under UV-irradiation at low temperatures (< 130°C) and used as the bottom electrode of an organic photodiode (OPD), consisting of a stacked layer of copper phthalocyanine (p-type material), perylene tetracarboxylic bisbenzimidazole (n-type material) and Aluminium tris(8-hydroxyquinoline). The performance of the photodiodes with printed ITO on plastic substrates could be improved by adding a smoothing layer of PEDOT/PSS (Baytron® P) on the ITO coated films and was then similar to the performance of photodiodes with semi-transparent gold as anode. These results demonstrate the suitability of the printed ITO layers as bottom electrode for organic photodiodes. Furthermore the influence of different treatments (forming gas and oxygen plasma treatment) of the ITO bottom electrode on the current-voltage characteristics of the OPDs was studied.

We report on a compact capacitance model that accurately describes both the gate length dependent and the gate length independent frequency dispersion observed in C-V curves for printed thin film transistors with non-ideal contacts. We also show that modeling the drain current with two adjacent subthreshold regions (instead of just one in the previous RPI TFT model) is needed to match the measured current-voltage characteristics. We show that Elmore model which accounts for channel length transit time is not sufficient for describing the frequency dispersion in C-V curves for printed TFTs and present the new Variable Dispersion Model (VDM). VDM reproduces the experimentally observed gate length independent dispersion arising due to the finite time of the electron exchange between the localized states in the mobility gap and the states above the mobility edge in amorphous semiconductors. The combined Elmore-VDM model has been implemented in AIM-Spice and showed good agreement with measured C-V data.

We have studied the effect of some of the possible deviations on the values of the extracted parameters of a specific OTFT model, considering OTFTs designed using P3HT as semiconductor layer, PMMA as insulator, bottom gate, and top gold contacts. Specifically, we have studied the influence of misposition or misalignment of the masks, the effect of imperfections of etching, and the effect of variations on the layer deposition process. These effects have been simulated using the Silvaco Athena software, and they have been modeled as horizontal shifts of the etching windows and variations of the layers thickness. Once the devices were defined, they were simulated using Silvaco Atlas, and parameter extraction was performed using a specifically developed algorithm. We have found a strong correlation among some of the physical parameters and the model parameters that may offer useful insight for process optimization. Moreover, strong correlations have been found also among the model parameters. We have used these results to develop a Monte Carlo model, suitable for statistical circuit simulation.

Inkjet printing is a promising and challenging technique that could potentially revolutionize large area and organic electronics fabrication. Inkjet systems are designed to construct devices and circuits drop by drop, which would lead to a new paradigm in electronics fabrication. However, inkjet technology for Printed Electronics is still under development and several challenges remain. While there is significant progress being made in the development of electronic devices, such as transistors or sensors, there is a lack of work on circuit and system level design. Designing devices and circuits implies a wide knowledge of process aspects, requiring a complex interaction among concepts, tools and processes coming from different science and engineering disciplines. An explicit methodology is needed to separate design from fabrication in a similar way as in silicon design, to design devices and systems without a deep knowledge of process and materials; thus making it possible to open up inkjet technology to a larger community and undergo more rapid design implementations. In this paper we present the main aspects of such a methodology and we discuss the key topics on inkjet technology that allow us to propose these new specific steps.

Pentacene and N,N'-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13H27) have been used as organic semiconductors for the fabrication of p-type and n-type organic thin-film transistors (OTFTs). Both types of semi-conductors are well-established and demonstrate good performance in singledevices, but few competitive results have been reported in complementary circuits. In this manuscript, we show the fabrication, electrical characterization and simulation of an organic complementary inverter using pentaceneand PTCDI-C13 as active semiconductors. Simulation was done using a model with physical aspects. The fitting of the parameters of the OTFT model is performed using an optimized parameter extraction technique which is using fuzzy logic to adjust the parameters to its optimal value. We also report good fitting of p-type and n-type parameters for the OTFT model and good results for DC transfer characteristics of the organic complementary inverter. In order to account for the presence of important parasitic elements, we show that the DC characteristics are best simulated using a transient analysis, instead of a DC.

We have developed an analytical model for polycrystalline-based organic thin-film transistors (OTFTs) that employs, as far as possible, new concepts on carrier injection to the conventional polysilicon model. The drain current equations, both in diffusion and drift regimes, predict the voltage and temperature dependencies on the various device and circuit parameters. Interestingly, upon direct comparison with previously developed disordered model, similarities between the two are not thought to be coincidental. The effect of gate voltage on surface potential is affected by the Fermi level pinning in the grain boundary, which is assumed to consist of mainly disordered material. This work also highlights the problem of using drift mobility, as an organic circuit design parameter, and consequently alternative quantities are proposed for simpler circuits such as an inverter. Upon validation of the model, relatively good fits are obtained with the experimental data on TIPS-based TFTs. The divergence at low drain voltages are thought to be associated with short channel and/or high contact resistance effects.