International Journal of High Speed Electronics and Systems

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

This work reports on the development of SiGe-BiCMOS technologies for mm-wave and THz high frequency applications. We present state-of-the-art performances for different SiGe heterojunction bipolar transistor (SiGe-HBT) developments as well as the evolution of complex BiCMOS technologies. With respect to different technology generations of high-speed SiGe-BiCMOS processes at IHP we discuss selected device modifications of the SiGe-HBT to achieve high frequency performances of a complex BiCMOS technology towards the 0.5 THz regime. We show the difference of high-frequency performance difference with respect to maximum achievable transit frequencies fT and oscillation frequencies f_max in comparison to RF-CMOS technologies and depict the required increase of additional process effort for the HBT-module integration for a 0.5 THz SiGe-BiCMOS technology. Moreover different high speed circuits are presented like broadband ICs for optical communication, high frequency circuits for wireless communication at 60 and 240 GHz, mm-wave radar circuits at 60 and 120 GHz as well as THz circuits operating at 245 GHz and 500 GHz for spectroscopic applications. All reviewed circuit examples are based on the discussed 130nm-SiGe-BiCMOS technologies and show their potential for a broad range of high-speed applications.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

We study theoretically the carrier transport and the plasmonic phenomena in the gated structures with dense lateral carbon nanotube (CNT) networks (CNT “felt”) placed between the highly-conducting slot line electrodes. The CNT networks under consideration consist of a mixture of semiconducting and metallic CNTs. We find the dispersion relations for the two-dimensional plasmons, associated with the collective self-consisted motion of electrons in the individual CNTs, propagating along the electrodes as functions of the net electron density (gate voltage), relative fraction of the semiconducting and metallic CNTs, and the spacing between the electrodes. In a wide range of parameters, the characteristic plasmonic frequencies can fall in the terahertz (THz) range. The structures with lateral CNT networks can used in different THz devices.

Recent developments in integrated on-chip nano-optomechanical systems are reviewed. Silicon-based nano-optomechanical devices are fabricated by a two-step process, where the first step is a foundry-enabled photonic circuits patterning and the second step involves in-house mechanical device release. We show theoretically that the enhanced responsivity of near-field optical transduction of mechanical displacement in on-chip nano-optomechanical systems originates from the finesse of the optical cavity to which the mechanical device couples. An enhancement in responsivity of more than two orders of magnitude has been observed when compared side-by-side with free-space interferometry readout. We further demonstrate two approaches to facilitate large-scale device integration, namely, wavelength-division multiplexing and frequency-division multiplexing. They are capable of significantly simplifying the design complexity for addressing individual nano-optomechanical devices embedded in a large array.