Computer Arithmetic

The Table of Contents for the book is as follows:

• About the Editor
• Preface
• Contents by Author
• Overview of Computer Arithmetic
• Part I: ERROR TOLERANT ARITHMETIC
  • Editors' Comments on Papers 1 Through 5
    • Error Detecting and Error Correcting Codes
    • Generalized Parity Checking
    • Error-Checking Logic for Arithmetic-Type Operations of a Processor
    • Arithmetic Algorithms for Error-Coded Operands
    • Error Detection and Correction for Addition and Subtraction, Through Higher Radix Extensions of Hamming Codes
• Part II: ON-LINE ARITHMETIC
  • Editor's Comments on Papers 6 Through 13
    • Signed-Digit Number Representations for Fast Parallel Arithmetic
    • On-Line Arithmetic: A Design Methodology and Applications in Digital Signal Processing
    • On-Line Algorithms for Division and Multiplication
    • Error Analysis of Certain Floating-Point On-Line Algorithms
    • Improved Normalization Results for Digit On-Line Arithmetic
    • Fully Digit On-Line Networks
    • On-Line Scheme for Computing Rotation Factors
    • On-the-Fly Conversion of Redundant into Conventional Representations
• Part III: VLSI ADDER IMPLEMENTATIONS
  • Editor's Comments on Papers 14 Through 18
    • Time-Component Complexity of Two Approaches to Multioperand Binary Addition
    • Some Optimal Schemes for ALU Implementation in VLSI Technology
    • An Area-Time Efficient NMOS Adder
    • Regular, Area-Time Efficient Carry-Lookahead Adders
    • Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection in a 32-bit VLSI Adder
• Part IV: VLSI MULTIPLIER IMPLEMENTATIONS
  • Editor's Comments on Papers 19 Through 24
    • A Monolithic 16 × 16 Digital Multiplier
    • Optimization of One-Bit Full Adders Embedded in Regular Structures
    • A VLSI Layout for a Pipelined Dadda Multiplier
    • A Very Fast Multiplication Algorithm for VLSI Implementation
    • A High-Speed Multiplier Using a Redundant Binary Adder Tree
    • A Sub-10-ns 16 × 16 Multiplier Using 0.6-μm CMOS Technology
• Part V: FLOATING-POINT VLSI CHIPS
  • Editor's Comments on Papers 25 Through 30
    • A High Performance Floating Point Coprocessor
    • 64 Bit Monolithic Floating Point Processors
    • A CMOS Floating Point Multiplier
    • A Single-Chip 80-Bit Floating Point Processor
    • VLSI Floating-Point Processors
    • Fast Multiply and Divide for a VLSI Floating-Point Unit
• Part VI: NUMBER REPRESENTATION
  • Editor's Comments on Papers 31 Through 37
    • The Residue Number System
    • A Formalization of Floating-Point Numeric Base Conversion
    • CADAC: A Controlled-Precision Decimal Arithmetic Unit
    • Finite Precision Rational Arithmetic: Slash Number Systems
    • Finite Precision Lexicographic Continued Fraction Number Systems
    • An Overflow/Underflow-Free Floating-Point Representation of Numbers
    • A Closed Computer Arithmetic
• Part VII: IMPLEMENTATIONS
  • Editor's Comments on Papers 38 Through 40
    • Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review
    • Designing Low-Power Circuits: Practical Recipes
    • The European Logarithmic Microprocessor
• Bibliography