Computer Arithmetic

Volume III

https://doi.org/10.1142/9467 | April 2015

Pages: 472

Edited by:
Earl E Swartzlander (University of Texas at Austin, USA) and
Carl E Lemonds (Qualcomm, Austin, USA)

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This volume is part of a reference set. To view or order the whole set, please visit the main page

Computer Arithmetic Volume III is a compilation of key papers in computer arithmetic on floating-point arithmetic and design. The intent is to show progress, evolution, and novelty in the area of floating-point arithmetic. This field has made extraordinary progress since the initial software routines on mainframe computers have evolved into hardware implementations in processors spanning a wide range of performance. Nevertheless, these papers pave the way to the understanding of modern day processors design where computer arithmetic are supported by floating-point units.

The goal of Volume III is to collect the defining document for floating-point arithmetic and many of the key papers on the implementation of both binary and decimal floating-point arithmetic into a single volume. Although fewer than forty papers are included, their reference lists will direct the interested reader to other excellent work that could not be included here.

Volume III is specifically oriented to the needs of designers and users of both general-purpose computers and special-purpose digital processors. The book should also be useful to systems engineers, computer architects, and logic designers. It is also intended to serve as a primary text for a course on floating-point arithmetic, as well as a supplementary text for courses in digital arithmetic and high-speed signal processing.

This volume is part of a 3 volume set:

Computer Arithmetic Volume I
Computer Arithmetic Volume II
Computer Arithmetic Volume III

The full set is available for sale in a print-only version.

Contents:

Overview
Floating-Point Addition
Floating-Point Multiplication
Rounding
Fused Multiply Add
Floating-Point Division
Elementary Functions
Decimal Floating-Point Arithmetic

Readership: Graduate students and research professionals interested in computer arithmetic.

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Computer Arithmetic: Volume III

Pages:1–474

https://doi.org/10.1142/9789814651141

Preview Abstract

The Table of Contents for the book is as follows:

About the Editors
Preface
Contents by Author
Introduction
Part I: OVERVIEW
- Editors' Comments on Paper 1
  - IEEE Standard for Floating-Point Arithmetic
Part II: FLOATING-POINT ADDITION
- Editors' Comments on Papers 2 Through 7
  - Delay-Optimized Implementation of IEEE Floating-Point Addition
  - Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition
  - Reduced Latency IEEE Floating-Point Standard Adder Architectures
  - Leading-Zero Anticipatory Logic for High-Speed Floating-Point Addition
  - Leading Zero Anticipation and Detection — A Comparison of Methods
  - S/370 Sign-Magnitude Floating-Point Adder
Part III: FLOATING-POINT MULTIPLICATION
- Editors' Comments on Papers 8 Through 10
  - A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
  - A Dual Mode IEEE Multiplier
  - 167 MHz Radix-4 Floating-Point Multiplier
Part IV: ROUNDING
- Editors' Comments on Papers 11 Through 14
  - Rounding Algorithms for IEEE Multipliers
  - Systematic IEEE Rounding Method for High-Speed Floating-Point Multipliers
  - A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
  - Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder
Part V: FUSED MULTIPLY ADD
- Editors' Comments on Papers 15 Through 19
  - Design of the IBM RISC System/6000 Floating-Point Execution Unit
  - A 17 × 69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency
  - Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
  - Floating-Point Fused Multiply-Add with Reduced Latency
  - Floating-Point Fused Multiply-Add Architectures
Part VI: FLOATING-POINT DIVISION
- Editors' Comments on Papers 20 Through 25
  - Floating-Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor
  - High Performance Floating-Point Unit with 116 bit Wide Divider
  - High-Speed Double-Precision Computation of Reciprocal, Division, Square Root, and Inverse Square Root
  - 167 MHz Radix-8 Floating-Point Divide and Square Root Using Overlapped Radix-2 Stages
  - Division Algorithms and Implementations
  - Faithful Interpolation in Reciprocal Tables
Part VII: ELEMENTARY FUNCTIONS
- Editors' Comments on Papers 26 Through 32
  - Computation of Elementary Functions on the IBM RISC System/6000 Processor
  - Accurate and Monotone Approximations of Some Transcendental Functions
  - The K5 Transcendental Functions
  - Hardware Designs for Exactly Rounded Elementary Functions
  - Toward Correctly Rounded Transcendentals
  - Reciprocation, Square Root, Inverse Square Root and Some Elementary Functions Using Small Multipliers
  - Multipartite Table Methods
Part VIII: DECIMAL FLOATING-POINT ARITHMETIC
- Editors' Comments on Papers 33 Through 37
  - A Decimal Floating-Point Specification
  - Decimal Floating-Point: Algorism for Computers
  - A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoded Format
  - Decimal Floating-Point Multiplication
  - A Survey of Hardware Designs for Decimal Arithmetic

Earl E Swartzlander, Jr is a Professor of Electrical and Computer Engineering at the University of Texas at Austin, USA. He and his students conduct research in computer engineering with emphasis on application-specific processor design, high-speed computer arithmetic, embedded processor architecture, VLSI technology, and QCA technology (an emerging form of nanotechnology). Dr. Swartzlander holds degrees in Electrical Engineering from Purdue University, the University of Colorado, and the University of Southern California.

Prof. Swartzlander is a Fellow of the IEEE. He has received the IEEE Third Millennium Medal, the Distinguished Engineering Alumnus Award from the University of Colorado, the Outstanding Electrical Engineer and Distinguished Engineering Alumnus awards from Purdue University and the IEEE Computer Society Golden Core Award.

He was the Editor-in-Chief of the IEEE Transactions on Computers from 1990–1994 and was the founding Editor-in-Chief of the Journal of VLSI Signal Processing. In addition, he has served as an associate editor for the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the IEEE Journal of Solid-State Circuits.

Carl E Lemonds, Jr is a Principal Member of Technical Staff at Qualcomm in Austin, Texas, USA. He is a member of Qualcomm's DSP design group working in logic design. Prior to Qualcomm, Mr Lemonds held several different design positions at AMD in Austin. In his career, he has been a design engineer at Intel, Cyrix and Texas Instruments. He holds bachelor and master degrees in Electrical Engineering from the University of Missouri at Columbia, USA.