Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.