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In this paper, we propose a new architecture for analog-to-digital converters (ADCs) using multistate spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFETs are multiple quantum coupled well devices, where the wells are stacked vertically and the electron wavefunction switches from one well to another with the change in gate voltage. Quantum mechanical simulations of 3-well InGaAs-AlInAs SWSFET structures are presented. The designs and simulations of 2-bit and 3-bit ADCs using SWSFETs result in low power consumption and reduced device count which improves the speed of the data conversion.

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

This paper presents the design and modeling of AND/OR logic gate using one high-mobility n-channel spatial wave-function switched field-effect transistor (n-SWS-FET), which provide a significant reduction of cell area and power dissipation. In SWSFET, the channel between source and drain has two or more quantum well (QW) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum well layers and it causes the switching of charge carriers from one channel to other channel of the SWS device. This switching property promises to build AND/OR logic gate with one n-SWS-FET transistor, where Complementary Metal Oxide Semiconductor (CMOS) AND/OR gate is built by 6 transistors. The proposed gate configures as AND/OR by change sources signal. The SWS-FET device with two well Si/Si_0.5Ge_0.5 has been modeled using Berkeley Short-channel IGFET Model (BSIM4.6.0) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for AND/OR logic and used to replace a conventional CMOS logic.

This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance g_m and channel conductance g_D using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.

This paper presents the design and modeling of AND/OR logic gate using one high-mobility n-channel spatial wave-function switched field-effect transistor (n-SWS-FET), which provide a significant reduction of cell area and power dissipation. In SWSFET, the channel between source and drain has two or more quantum well (QW) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum well layers and it causes the switching of charge carriers from one channel to other channel of the SWS device. This switching property promises to build AND/OR logic gate with one n-SWS-FET transistor, where Complementary Metal Oxide Semiconductor (CMOS) AND/OR gate is built by 6 transistors. The proposed gate configures as AND/OR by change sources signal. The SWS-FET device with two well Si/Si0.5Ge0.5 has been modeled using Berkeley Short-channel IGFET Model (BSIM4.6.0) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for AND/OR logic and used to replace a conventional CMOS logic.

This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance g_m and channel conductance g_D using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.