A Novel One SWS-FET Transistor for AND/OR Logic Gate

This paper presents the design and modeling of AND/OR logic gate using one high-mobility n-channel spatial wave-function switched field-effect transistor (n-SWS-FET), which provide a significant reduction of cell area and power dissipation. In SWSFET, the channel between source and drain has two or more quantum well (QW) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum well layers and it causes the switching of charge carriers from one channel to other channel of the SWS device. This switching property promises to build AND/OR logic gate with one n-SWS-FET transistor, where Complementary Metal Oxide Semiconductor (CMOS) AND/OR gate is built by 6 transistors. The proposed gate configures as AND/OR by change sources signal. The SWS-FET device with two well Si/Si_0.5Ge_0.5 has been modeled using Berkeley Short-channel IGFET Model (BSIM4.6.0) and Analog Behavioral Model (ABM), the model is suitable for transient analysis at circuit level. This model is optimized for AND/OR logic and used to replace a conventional CMOS logic.