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Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs

    https://doi.org/10.1142/S0129156420400133Cited by:2 (Source: Crossref)
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    This article is part of the issue:
    Special Issue on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications
    Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

    Abstract

    This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

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