International Journal of High Speed Electronics and Systems

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

Metamorphic semiconductor devices often utilize compositionally-graded buffer layers for the accommodation of the lattice mismatch with controlled threading dislocation density and residual strain. Linear or step-graded buffers have been used extensively in these applications, but there are indications that sublinear, superlinear, S-graded, or overshoot graded structures could offer advantages in the control of defect densities. In this work we compare linear, step-graded, and nonlinear grading approaches in terms of the resulting strain and dislocations density profiles using a state-of-the-art model for strain relaxation and dislocation dynamics. We find that sublinear grading results in lower surface dislocation densities than either linear or superlinear grading approaches.

Strained-layer superlattices (SLSs) have been used to modify the threading dislocation behavior in metamorphic semiconductor device structures; in some cases they have even been used to block the propagation of threading dislocations and are referred to in these applications as “dislocation filters.” However, such applications of SLSs have been impeded by the lack of detailed physical models. Here we present a “zagging and weaving” model for dislocation interactions in multilayers and strained-layer superlattices, and we demonstrate the use of this model to the threading dislocation dynamics in InGaAs/GaAs (001) structures containing SLSs.

Since the invention of dislocation sidewall gettering (DSG) in 2000 the technique has been applied extensively in infrared focal-plane arrays and flat-panel displays. However, development of DSG technology has been guided mostly by empirical trials due to the lack of detailed physical models. Here we demonstrate the application of a dislocation dynamics model to evaluate DSG approaches in both ZnS_ySe_1-y/GaAs (001) and InGa_xAs_1-x/GaAs (001) heterostructures. We find that the effectiveness of DSG is strongly dependent on composition in both material systems.

In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocation dynamics in InGaAs/GaAs (001) heterostructures. Current approaches are all based on the extension of the original Dodson and Tsao plastic flow model to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent break-throughs have greatly enhanced the utility of these modeling approaches in four respects: i) pinning interactions are included in graded and multilayered structures, providing a better description of the limiting strain relaxation as well as the dislocation sidewall gettering; ii) a refined model for dislocation-dislocation interactions including zagging enables a more accurate physical description of compositionally-graded layers and step-graded layers; iii) inclusion of back-and-forth weaving of dislocations provides a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices or overshoot graded layers; and iv) the compositional dependence of the model kinetic parameters has been elucidated for the InGaAs material system, allowing more accurate modeling of heterostructures with wide variations in composition. We will describe these four key advances and illustrate their applications to heterostructures of practical interest.

Continuous enhancement of the performance of energy harvesters in recent years has broadened their arenas of applications. On the other hand, ample availability of IoT devices has made radio frequency (RF) a viable source of energy harvesting. Integration of a maximum power point tracking (MPPT) controller in RF energy harvester is a necessity that ensures maximum available power transfer with variable input power conditions. In this paper, FPGA implementation of a machine learning (ML) model for maximum power point tracking in RF energy harvesters is presented. A supervised learning-based ML model-feedforward neural network (FNN) has been designed which is capable of tracking maximum power point with optimal accuracy. The model was designed using stochastic gradient descent (SGD) optimizer and mean square error (MSE) loss function. Simulation results of the VHDL translated model demonstrated a good agreement between the expected and the obtained values. The proposed ML based MPPT controller was implemented in Artix-7 Field Programmable Gate Array (FPGA).

In-memory computing is an emerging technique to fulfill the fast growing demand for high-performance data processing. This technique provides fast processing and high throughput by accessing data stored in the memory array rather than dealing with complicated operation and data movement on hard drive. For data processing, the most important computation is dot product, which is also the core computation for applications such as deep learning neuron networks, machine learning, etc. As multiplication is the key function in dot product, it is critical to improve its performance and achieve faster memory processing. In this paper, we present a design with the ability to perform in-memory multi-bit multiplications. The proposed design is implemented by using quantum-dot transistors, which enable multi-bit computations in the memory cell. Experimental results demonstrate that the proposed design provides reliable in-memory multi-bit multiplications with high density and high energy efficiency. Statistical analysis is performed using Monte Carlo simulations to investigate the process variations and error effects.

Multi-analyte chemical sensor aims to transform subtle variations in multiple analytes’ physical or chemical properties into distinct output signals. Chemically responsive nanostructure array (nanoarray) promises as a competitive sensor platform due to its robust physical properties, tunable chemical composition, and high surface area for analyte interaction. Specifically, the well-defined size, shape, and tunable surface structure and properties make it feasible to develop either new sensing modes on single device or integrated multi-modular sensors. In conjunction with the well-developed resistor-type sensors and sensor arrays, the complementary utilization of and intercorrelation with the electrochemical, optical, voltammetry modes in the multi-modular sensing strategies could provide multi-dimensional measurements to different analytes in a complex mixture form, where species information could be accurately and robustly separated from spatially collective responses. This review intends to provide a survey of the recent progress on multi-analyte sensing strategies and their unique structure design, as well as the related sensing mechanics in interaction of analytes and sensitizer and the behind mechanism for analytes’ differentiation.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).

This paper proposes a novel scheme for inter-connecting IOT devices with servers. To overcome the drawbacks and other shortcomings of existing IoT network schemes, a new approach to IoT device certification and inter-connecting IoT devices to other network devices (e.g., aggregators and servers) is described. The proposed approach ensures that the overall IoT network is “hardened” against attack and meets the stringent requirements of mission critical applications.

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

Humanoid robots are employed in a wide range of fields to replicate human actions. This paper presents the mechanism, configuration, mathematical modeling, and workspace of a 3D printed humanoid robot – Amaranthine. It also discusses the potential scope of humanoid robots in the present day and future. Robots can be programmed for automation as per the demand of the task or operations to be performed. Humanoid robots, while being one of the small groups of service robots in the current market, have the greatest potential to become the industrial tool of the future. Introducing a Humanoid Robot-like Amaranthine holds huge scope majorly in the fields of medical assistance, teaching aid, large industries where heavy-duty operations require application-specific software, etc. Amaranthine was 3D printed and assembled at the RISC Lab of University of Bridgeport.

With the development of inkjet-/3D-/4D-printing additive manufacturing technologies, flexible 3D substrate with complex structures can be patterned with dielectric, conductive and semi-conductive materials to realize novel RF designs. This paper provides a review of state-of-the-art additively manufactured passive RF devices including antennas and frequency selective surfaces (FSS), couplers, where origami-inspired structure enables unprecedented capabilities of on-demand continuous frequency tunability and deployability. This paper also discusses additively manufactured active RF modules and systems such as inkjet printed RF energy harvester system with high sensitivity and efficiency for Internet of Things (IoT), smart cities and wireless sensor networks (WSN) applications, inkjet-printed RF front ends, and inkjet-printed mm-wave backscatter modules.

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance g_m and channel conductance g_D using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.