Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.