Narrow Results

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM.

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM.