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Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

Unlike conventional FETs, spatial wavefunction switched (SWS)-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The aim of this paper is to present 4-states/2-bit output-input transfer characteristics using two Si/SiGe quantum well channels configured as CMOS using n- and p-channel spatial wavefunction switched field-effect transistors (SWS-FETs). Quantum simulations show switching of wavefunctions as the gate voltage is increased from lower Si quantum well to the upper well in n-channel and from upper SiGe quantum well to lower well in the p-channel. The inverter transfer characteristic and current switching are obtained by integrating BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). The simulation shows current flow only during switching.

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

This paper presents a comprehensive analysis of power dissipation and propagation delay in 2-bit SRAM configurations ranging from 7T to 10T, building upon previous work on 6T 2-bit/4-state SWSFET SRAM designs. The study compares the performance of SWSFET SRAMs with CMOS-based 2-state SRAMs [7], highlighting the former’s significant advantages in speed and power consumption. Utilizing Cadence simulations and models such as Analog Behavioral Model (ABM) and EKV (Enz–Krummenacher–Vittoz), the analysis incorporates real-world 0.18-$\mu$m technology considerations. The research explores the design nuances of 7T–10T SRAM configurations using SWS-FETs, leveraging their unique characteristics like vertically stacked quantum well/quantum dot channels. Power dissipation analysis reveals varying trends across different SRAM configurations, with notable shifts in voltage changes during transitions. Similarly, propagation delay assessments showcase diverse durations for different voltage transitions, underscoring the impact of SRAM configuration changes on efficiency and complexity. In addition, parasitic capacitance is crucial for optimizing the performance, power efficiency, and reliability of SRAM cells. In these circuits an internal storage parasitic capacitance of 1fF has been considered to evaluate its effects through simulation-based analysis during the memory cell design process. The findings contribute valuable insights into the trade-offs involved in SRAM design, particularly concerning power dissipation and propagation delay, and are presented. Overall, this study sheds light on the promising potential of SWS-FETs for enhancing memory circuitry performance.

Unlike conventional FETs, spatial wavefunction switched (SWS)-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The aim of this paper is to present 4-states/2-bit output-input transfer characteristics using two Si/SiGe quantum well channels configured as CMOS using n- and p-channel spatial wavefunction switched field-effect transistors (SWS-FETs). Quantum simulations show switching of wavefunctions as the gate voltage is increased from lower Si quantum well to the upper well in n-channel and from upper SiGe quantum well to lower well in the p-channel. The inverter transfer characteristic and current switching are obtained by integrating BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). The simulation shows current flow only during switching.

Multi-state room temperature operation of SiO_x-cladded Si quantum dots (QD) and GeO_x-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density n_QM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

This paper presents a comprehensive analysis of power dissipation and propagation delay in 2-bit SRAM configurations ranging from 7T to 10T, building upon previous work on 6T 2-bit/4-state SWSFET SRAM designs. The study compares the performance of SWS-FET SRAMs with CMOS-based 2-state SRAMs [7], highlighting the former’s significant advantages in speed and power consumption. Utilizing Cadence simulations and models such as Analog Behavioral Model (ABM) and EKV (Enz–Krummenacher–Vittoz), the analysis incorporates real-world 0.18-µm technology considerations. The research explores the design nuances of 7T–10T SRAM configurations using SWS-FETs, leveraging their unique characteristics like vertically stacked quantum well/quantum dot channels. Power dissipation analysis reveals varying trends across different SRAM configurations, with notable shifts in voltage changes during transitions. Similarly, propagation delay assessments showcase diverse durations for different voltage transitions, underscoring the impact of SRAM configuration changes on efficiency and complexity. In addition, parasitic capacitance is crucial for optimizing the performance, power efficiency, and reliability of SRAM cells. In these circuits an internal storage parasitic capacitance of 1 fF has been considered to evaluate its effects through simulation-based analysis during the memory cell design process. The findings contribute valuable insights into the trade-offs involved in SRAM design, particularly concerning power dissipation and propagation delay, and are presented. Overall, this study sheds light on the promising potential of SWS-FETs for enhancing memory circuitry performance.

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWS-FET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.