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SPATIAL WAVEFUNCTION-SWITCHED (SWS)-FET: A NOVEL DEVICE TO PROCESS MULTIPLE BITS SIMULTANEOUSLY WITH SUB-PICOSECOND DELAYS

F. C. JAIN

Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA

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J. CHANDY

Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA

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B. MILLER

Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA

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E-S. HASANEEN

Electrical Engineering Department, El-Minia University, Egypt

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, and

E. HELLER

RSoft Design Group, Ossining, NY 10562, USA

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https://doi.org/10.1142/S0129156411006933Cited by:19 (Source: Crossref)

Abstract

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

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