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Simulation and Comparative Study of Propagation Delay in Multi-Channel Quantum SWS-CMOS-Based Inverters Using II–VI Gate Insulator

A. Almalki

https://orcid.org/0009-0001-1954-4644

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

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B. Saman

https://orcid.org/0000-0001-6917-5763

Department of Electrical Engineering, College of Engineering, Taif University, Saudi Arabia

E-mail Address: Saman@tu.edu.sa

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R. H. Gudlavalleti

https://orcid.org/0000-0002-7727-8030

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

Biorasis Inc., Storrs, CT, USA

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J. Chandy

https://orcid.org/0000-0003-3449-3205

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

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E. Heller

https://orcid.org/0009-0005-4405-7089

Synopsys Inc., Ossining, NY 10562, USA

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, and

F. C. Jain

https://orcid.org/0000-0003-3961-6665

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

E-mail Address: faquir.jain@uconn.edu

Corresponding author.

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https://doi.org/10.1142/S0129156424400585Cited by:0 (Source: Crossref)

This article is part of the issue:

Special Issue on “Nanoelectronics, Nanophotonics, Quantum and Emerging Technologies”
Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Abstract

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO₂ and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

Keywords:

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