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This work investigates the working of an inverter and a ring oscillator using symmetrical junction nonaligned double gate field effect transistors (NADGFETs). The performance of the circuits was investigated with two dielectric (k) materials, i.e., silicon dioxide (low-$k,k=3.9$) and hafnium dioxide (high-$k,k=24$), into the device’s gate oxide. Simulations were performed in the TCAD Sentaurus Sdevice mixed-mode environment, and the circuit’s response is analyzed as a function of supply voltage, load capacitance and temperature. Additionally, this work evaluates the effect of changes in device parameters on the performance of inverter and oscillator configuration. Using the graphical method, the optimal supply voltage of the inverter was determined, with a 0.66V optimal supply, the propagation delay of the inverter with low-k and high-k materials was 6.1ps and 7.5ps, respectively. The inverters’ power delay product with low-k materials is 45.38 aJ and with high-k materials, it is 70.37 aJ. For a better insight into the nonaligned double gate devices’ performance, a 5-stage ring oscillator was simulated. The oscillator circuit gives an output voltage/oscillation frequency of 1.18 V/67 GHz and 1.205V/44 GHz, with low-k and high-k materials, respectively, at 1.0V supply. The oscillator with low-k gate oxide shows a 34.3% increase in oscillation frequency. From the results, it can be concluded that the nonaligned devices with low-k gate oxide will give an improved response in low-power and high-frequency applications.

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO₂ and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V_CC) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V_CCs to different elements.

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

This paper introduces a new technique for analyzing the behavior of global interconnects in FPGAs, for nanoscale technologies. Using this new enhanced modeling method, new enhanced accurate expressions for calculating the propagation delay of global interconnects in nano-FPGAs have been derived. In order to verify the proposed model, we have performed the delay simulations in 45 nm, 65 nm, 90 nm, and 130 nm technology nodes, with our modeling method and the conventional Pi-model technique. Then, the results obtained from these two methods have been compared with HSPICE simulation results. The obtained results show a better match in the propagation delay computations for global interconnects between our proposed model and HSPICE simulations, with respect to the conventional techniques such as Pi-model. According to the obtained results, the difference between our model and HSPICE simulations in the mentioned technology nodes is (0.29–22.92)%, whereas this difference is (11.13–38.29)% for another model.

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO₂ and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.