Special Issue on 23^rd Connecticut Microelectronics and Optoelectronics Consortium Symposium (CMOC-2014) April 9, Connecticut, USA; Edited by F. Jain, C. Broadbridge and H. TangNo Access

Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs

Pial Mirdha

Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Unit 4157, Storrs, CT 06269, USA

E-mail Address: pial.mirdha@uconn.edu

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Murali Lingalugari

Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Unit 4157, Storrs, CT 06269, USA

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Evan K. Heller

Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Unit 4157, Storrs, CT 06269, USA

Synopsys Inc., Ossining, NY 10562, USA

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John A. Chandy

Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Unit 4157, Storrs, CT 06269, USA

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Faquir C. Jain

Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Way, Unit 4157, Storrs, CT 06269, USA

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https://doi.org/10.1142/S0129156415200116Cited by:1 (Source: Crossref)

Abstract

In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.