3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.