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A Modeling Study of Dislocation Sidewall Gettering in II-VI and III-V Semiconductor Heterostructures

Tedi Kujofsa

Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA

E-mail Address: tedi.kujofsa@gmail.com

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and

J. E. Ayers

Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA

E-mail Address: john.ayers@uconn.edu

Corresponding author.

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https://doi.org/10.1142/S0129156420400042Cited by:0 (Source: Crossref)

This article is part of the issue:

Special Issue on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications
Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Abstract

Since the invention of dislocation sidewall gettering (DSG) in 2000 the technique has been applied extensively in infrared focal-plane arrays and flat-panel displays. However, development of DSG technology has been guided mostly by empirical trials due to the lack of detailed physical models. Here we demonstrate the application of a dislocation dynamics model to evaluate DSG approaches in both ZnS_ySe_1-y/GaAs (001) and InGa_xAs_1-x/GaAs (001) heterostructures. We find that the effectiveness of DSG is strongly dependent on composition in both material systems.

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