International Journal of High Speed Electronics and Systems

Viral infections (like different types of influenza virus) are becoming alarmingly common often leading to epidemics. Since Viruses can multiply from genomic materials it can spread the infection quickly as well as cause other complications like birth defects, autoimmune disease and even cancer. Diagnostics of viral infection traditionally is performed using antigen-antibody reaction, which is time consuming and labor intensive. Also, viral infections can be latent or show false negative results when antibody reaction is tested. In-situ direct hybridization detection is possible by expensive, long and difficult radiation-based methods. Our group has developed a Carbon Nanotube (CNT) & Graphene based Bionanosensor (BNS) for rapid and direct detection of specific DNA sequences. In this technique, single-stranded (ss) DNA probe (known as priming) is immobilized on a substrate. This recognizes a specific complementary target DNA in a sample solution and gets hybridized leading to a detectable electrical signal. In this study we have expanded the scope of this BNS by using it to detect quick in-situ RNA hybridization. A sample of RNA was tested simultaneously in an array of 4 biosensors (each primed by the complementary sequence). The resistance across each of the biosensors was measured with a self-designed, feed-back controlled, balanced Wheatstone bridge circuit with an Arduino interface. A specific pattern related to hybridization was observed and a weighted average performed over 30 experiments. The sensors primed with the forward RNA was able to detect the complementary sequence in a mixed sample in 10 minutes from the starting time.

Pathogen diseases cause considerable loses in production of food which impact human health from diverse bacterial/viral infections. Precise spotting and diagnosis of such infectious disease is significant to prevent it from further outbreak issues. Moreover, to detect this kind of diseases at an early stage with highly sensitive and selective basis is necessary to avoid the spread of invasive pathogens. The conventional methods such as ELISA, PCR techniques are currently in use to diagnose bacterial/viral disease with high throughput. Though these diagnostic techniques assist in detect and identify the diseases, there are few modern challenges to be meet in order to make this diagnostic more effective in recent days. In this paper, our designed device consists of Bionanosensor works on nucleic acid-based testing provides result with high specificity and selectivity which is vital for early stage identification in a rapid real-time effective manner

Carbon nanotubes (CNTs) are a viable product for many different markets. One specific area of promise is the use of CNTs in supercapacitors. The CNT synthesis is a two-step process with the first being the formation of a thin film layer. The thin film substrate is created by means of the Thermal Evaporation Physical Vapor Deposition (TPVD) process. After the thin film substrate is deposited, the CNTs are grown in a Chemical Vapor Deposition (CVD) growth chamber. Analysis of the thin film substrate and CNTs is performed primarily using Scanning Electron Microscopy (SEM). The results show the inclusion of ultrapure water in the CVD process contributed to the success of CNT growth. Multiple prong CNT grow is seen for CVDs trails of silver thin film layer deposited on silicon substrates. The silver nanoparticle had a large diameter with an acute contact angle. The single prong growth indicates the iron nanoparticles formed an obtuse contact angle due to the amorphic surface of alumina substrate. The focus of this project is to explore and investigate different materials and conditions for optimal CNT synthesis in the hopes of creating a uniform forest of vertically aligned carbon nanotubes.

This publication provides an overview of additive manufacturing techniques including Inkjet, 3D and 4D printing methods. The strengths, opportunities and advantages of this array of manufacturing techniques are evaluated at different scales. We discuss first the applicability of additive manufacturing techniques at the device scale including the development of origami inspired tunable RF structures as well as the development of skin-like conformal, flexible systems for wireless/IoT, Smartag and smart city applications. We then discuss application at the package scale with on package printed antennas and functional packaging applications. Following this, there is a discussion of additive manufacturing techniques in applications at the die scale such as 3D printed interconnects. The paper is concluded with an outlook on future advancements at the component scale with the potential for fully printed passive components.

We conducted a modeling study of the threading dislocation behavior in chirped and unchirped InGaAs/GaAs (001) strained-layer superlattices (SLSs) using a Dodson & Tsao / Kujofsa & Ayers (DTKA) type plastic flow model. Four types of SLSs were investigated: type I was chirped using compositional modulation, type II was chirped using layer thickness modulation, type III was unchirped with alternating layers of InGaAs and GaAs, and type IV was unchirped with alternating layers of InGaAs having two different compositions. Generally the surface and average values of the dislocation density decreased with increasing total thickness. The dependence on top indium composition was more complex, due to dislocation compensation and multiplication effects, but for type II and IV superlattices, the average and surface threading dislocation densities increased in nearly monotonic fashion with top indium composition. Based on these results, the compositionally-modulated chirped (type I) and InGaAs/GaAs unchirped (type III) superlattices appear to be best suited as buffer layers for metamorphic devices, while the chirped superlattices with layer thickness modulation (type II) and InGaAs/InGaAs unchirped (type IV) superlattices appear to be poorly suited for use as buffer layers for devices containing high indium content.

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Blockchain technology is believed to be a highly secured solution for it is a decentralized ledger guarded by cryptographic techniques. However, the recent successful ‘51% Attack’ [1] on Ethereum Blockchain network, raised concerns regarding the trustworthiness of this technology. This paper addresses the causes and solutions to that attack. Private Transactions like the techniques implemented in Parity Ethereum and Quorum are introduced. Proof of Stack (POS) is another approach using economic incentives instead of intensive computations to guard against attacks while reducing power consumed. They are considered mitigation to the ‘51% Attack’. The use of Second Factor Authentication at the Smart Contract level is also addressed.

In this paper a comparative in-situ ellipsometric analysis is carried out on plasma-assisted ALD-grown III-nitride (AlN, GaN, and InN) films. The precursors used are TMA, TMG, and TMI for AlN, GaN, and InN respectively, while Ar is used as purge gas. For all of the films N₂/H₂/Ar plasma was used as the co-reactant. The work includes real-time in-situ monitored saturation curves, unit ALD cycle analysis, and >500 cycle film growth runs. In addition, the films are grown at different substrate temperatures to observe the impact of temperature not only on the growth rate but on how it influenced the precursor chemisorption, ligand removal, and nitrogen incorporation surface reactions. All three nitride films confirm fairly linear growth character. The growth rate per cycle (GPC) for each film is also measured with respect to rf-plasma power to obtain the surface saturation conditions during ALD growth. The real-time in-situ monitoring of the film growth can really be beneficial to understand the atomic layer growth and film formation in each individual ALD cycle.

The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive hardware attack obtaining information from IC chips always violates the IP rights of vendors. This paper proposes a new security mechanism implanted ROM design to address the vulnerability to reverse energy attacks. Irreversible via in ROM layout transform triggered by reverse engineering completely changes the electrical properties and the physical structure of ROMs that determine the stored data. Newly-created patten will significantly increase the difficulty of reverse engineering, even lead the attackers to another working function mode. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Two widely used ROM scheme cases have been studied to test the design method and its effectiveness. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.

CCS Concepts: Security and privacy → Hardware reverse engineering; Hardware → Hard and soft IP

Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.

Transient performance of nanowire memristors realized using different material systems is discussed. The approach is validated by comparing simulated results with experimental data obtained for a ZnO nanowire memristor. The ZnO nanowire memristors demonstrate bipolar resistive switching with an R_OFF/R_ON ratio of 684 that is 3 times higher than the previous best report. The transient switching model, derived from the physical mechanisms for memristor switching, show a material dependent switching delay greatly influenced by the mobility of the oxygen vacancies. Measured switching delay of 372 µs for ZnO memristor show excellent agreement with the simulated data. The switching delays for other material systems, namely – TiO_x, TaO_x, HfO_x, and ZrO_x are calculated to be 2.5 s, 5.5 ns, 11.8 ps, and 7.15 ps, respectively, for identical device geometry (length 2 µm and diameter 300 nm). Upon scaling devices down to 50 nm, the delay is observed to decrease by 3-4 orders of magnitude. ZrO_x based memristors showed the shortest switching delay owing to a mobility as high as 370 cm²/V-s. Experimental data for ZnO memristors suggest rise and fall times shorter than 7 µs and 10 ns, respectively. Ultralow switching power of 261 µW and 155 µW are achieved for SET and RESET switching, respectively. Measured switching energy less than 83 nJ and slew rates greater than 0.02 V/µs are attained.

This paper presents novel multi-bit static random access memories (SRAMs) using spatial wave-function switched (SWS) FETs. A SWS-FET comprises of two or more vertically stacked quantum well channels while having a single gate and multiple sources and drains. Simulations are presented for 2-bit static random access memories (SRAMs) using cross-coupled 4-states SWS-CMOS inverters. The CMOS inverters are based on 4-state SWS FETs using two Si/SiGe quantum well channels. SWS-structures having 4-quantum well channels processing 8-states/3-bit are described. Logic simulation of multi-bit latches and registers is also presented. Multi-bit CMOS SWS-SRAMs and registers, integrated with logic, and quantum dot nonvolatile random access memories (QD-NVRAMs) presents a new paradigm for low power, high-speed computing.

This paper presents simulation of spatial wavefunction switched (SWS) field-effect transistors (FETs) comprising of two vertically stacked quantum dot channels. An analog behavior model (ABM) was used to compare the experimental I-V characteristics of a fabricated QD-SWS-FET. Each channel consists of two quantum dot layers and are connected to the dedicated drains D2 and D1, respectively. The fabricated SWS-FET has one source and one gate. The ABM simulation models SWS-FET comprising of two independent conventional BSIM FETs with their (W/L) ratios, capacitances and other device parameters. The agreement in simulation and experimental data will advance modeling of SWS based adders, logic gates and SRAMs.

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.