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EQUALIZERS FOR HIGH-SPEED SERIAL LINKS

    https://doi.org/10.1142/9789812774583_0007Cited by:0 (Source: Crossref)
    Abstract:

    In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.