SIMULATIONS OF FIELD-PLATED AND RECESSED GATE GALLIUM NITRIDE-BASED HETEROJUNCTION FIELD-EFFECT TRANSISTORS

We report on two-dimensional isothermal simulations of recessed gate and field-plated AlGaN-GaN HFETs with submicron gates. The optimization of the recessed gate shape allows us to reduce the electric field at the drain-side gate edge by approximately 30%. Our simulations reveal a dramatic increase of the effective gate length with increasing drain-to-source bias with a commensurate decrease of the cutoff frequency (up to 40% decrease for 50V). To improve the cutoff frequency for the high drain-to-source bias, we suggest using the second field plate connected to the drain with a small gap between the two field plates. In this design, the electric field in the gap between the gate and the drain field plate is higher leading to a significant reduction of the effective gate length and, as a consequence, to an increase in the cutoff frequency at high drain-to-source biases (compared to the conventional design).