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Microwave noise technique is applied to study energy dissipation in an AlN/GaN heterostructure containing a two-dimensional electron gas channel. Measurements of the dissipated power and the noise temperature are performed at 80 K lattice temperature in the electric field range up to 40 kV/cm. The energy relaxation time is found to decrease from 40 ps to 0.55 ps when the bias is increased. The experimental data are discussed in the electron temperature approximation assuming electron energy dissipation on optical phonons and hot-phonon effects. Dependencies of the hot-phonon number and the hot-phonon temperature on the hot-electron temperature are deduced. The frequency cutoff imposed by the limited energy dissipation through optical phonons is estimated.

We report on two-dimensional isothermal simulations of recessed gate and field-plated AlGaN-GaN HFETs with submicron gates. The optimization of the recessed gate shape allows us to reduce the electric field at the drain-side gate edge by approximately 30%. Our simulations reveal a dramatic increase of the effective gate length with increasing drain-to-source bias with a commensurate decrease of the cutoff frequency (up to 40% decrease for 50V). To improve the cutoff frequency for the high drain-to-source bias, we suggest using the second field plate connected to the drain with a small gap between the two field plates. In this design, the electric field in the gap between the gate and the drain field plate is higher leading to a significant reduction of the effective gate length and, as a consequence, to an increase in the cutoff frequency at high drain-to-source biases (compared to the conventional design).

We have studied the effect of different structural designs of double gate MOSFETs (DG–MOSFETs) and carbon nanotube field effect transistors (CNTFETs) on the cutoff frequency (f_T). The effects of metallic contacts with Schottky barriers, gate work function, dual material gate (DMG), halo doped channel and lightly doped drain and source (LDDS) architectures on the f_T have been investigated for DG–MOSFETs and CNTFETs and the design dependent f_T for both types of transistors has been studied for the first time. The simulations are based on the Schrödinger–Poisson solvers developed for each nanotransistor separately. The ballistic limit has been studied as the ultimate performance limit of the DG–MOSFETs and CNTFETs. The results of this paper, for the first time, show how some designations used for modification of short channel effects or current–voltage characteristics affect the f_T. The results revealed that the cutoff frequencies of both types of the transistors exhibit the same behavior with changing design parameters. We have shown that the Schottky barriers, parasitic capacitances and halo doping reduce the f_T and have proposed the DMG and LDDS artchitectures as ways to increase the f_T for DG–MOSFETs and CNTFETs for the first time.

In this paper, a new structure, step–linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

By employing the characteristics matrix method, we have investigated the transmission properties of one-dimensional dielectric–semiconductor metamaterial photonic crystals (PC) at Terahertz (THz) range theoretically. The numerical results show the appearance of cutoff frequency within THz range. Furthermore, the thicknesses of the constituents materials and the filling factor have a significant effect on the cutoff frequency. The proposed structure may be useful in many applications, particularly in THz frequency regions.

In this paper, an efficient structure with lightly doped drain region is proposed for p-i-n graphene nanoribbon field effect transistors (LD-PIN-GNRFET). Self-consistent solution of Poisson and Schrödinger equation within Nonequilibrium Green’s function (NEGF) formalism has been employed to simulate the quantum transport of the devices. In proposed structure, source region is doped by constant doping density, channel is an intrinsic GNR, and drain region contains two parts with lightly and heavily doped doping distributions. The important challenge in tunneling devices is obtaining higher current ratio. Our simulations demonstrate that LD-PIN-GNRFET is a steep slope device which not only reduces the leakage current and current ratio but also enhances delay, power delay product, and cutoff frequency in comparison with conventional PIN GNRFETs with uniform distribution of impurity and with linear doping profile in drain region. Also, the device is able to operate in higher drain–source voltages due to the effectively reduced electric field at drain side. Briefly, the proposed structure can be considered as a more reliable device for low standby-power logic applications operating at higher voltages and upper cutoff frequencies.

By using the transfer matrix method (TMM), we theoretically explore the transmittance properties and cutoff frequency of one-dimensional photonic crystal (1DPCs) within the terahertz frequency region. The present structure consists of high-temperature superconductor and semiconductor layers. The results of the calculations represent the effects of various parameters on the cutoff frequency. We have used the two-fluid model as well as the Drude model to describe the permittivity of superconductor and semiconductor. Further, we consider that the permittivity of both the materials is depending on the hydrostatic pressure. The present results show that with the increasing of different parameters as the operating temperature, the thickness of semiconductor, and the filling factor of semiconductor, then the cutoff frequency shift to lower frequencies regions. By the increasing of superconductor thickness, hydrostatic pressure, doping concentration and filling factor of the superconductor, we found the cutoff frequency shifts to higher frequency regions. These results indicate that cutoff frequency can be modified through these different parameters. Finally, the present design could be useful for many optical systems as the optical filter, reflector and photoelectronic applications in the Terahertz regime.

In this research, a one-dimensional photonic crystal with such a novel and simple design is introduced to serve as an efficient reflector for infrared (IR) wavelengths. The construction of the proposed photonic crystal design based on the gyroidal geometry is the mainstay of this research to investigate the total reflectivity through a wide band of IR wavelengths. In this regard, [Air/(A/B)¹⁰/substrate] is indeed the configuration of the suggested photonic crystal structure. The layer symbols, A and B represent two layers of silver with a gyroidal configuration in host materials of titanium dioxide and silicon, respectively. Meanwhile, our numerical findings demonstrate the existence of a cutoff feature at a wavelength of 1$\mu$m of the propagating electromagnetic waves. Moreover, the filling fraction of sliver through layers (A) and (B) provides a substantial role in the tunability of the cutoff frequency and the reflectivity of the structure as well. Then, we have taken into account how the host material’s thicknesses and refractive indices will affect the proposed structure’s reflectance. In particular, the refractive index of the host material could lead to a significant variation of the permittivities of the considered materials. Finally, we think that the proposed structure may be of a great interest in a variety of physical and engineering applications including the optical reflectors, smart windows and solar cells applications as well.

Half-T RC ladder networks (LNs) are proven to be first-order models of transmission lines (TLs) and interconnections. In this paper, the determination of LNs electrical characteristics, in terms of internal electrical parameters and number of cells, has allowed to calculate, in an approximated but very accurate way, the time delay and cutoff frequency of open-ended RC LN. Numerical examples on real designs confirm the validity of the proposed method in terms of robustness and accuracy.

In this paper, optimum transistor sizing of CMOS differential amplifier using tunicate swarm algorithm (TSA) is proposed. The designing of CMOS differential amplifier is activated to determine the best feasible design parameter values. This work proposes the optimized values of various parameters of a CMOS differential amplifier for better performance. TSA is chosen to optimize the circuit area. TSA has the ability to solve complex functions, like MOS transistor size and bias current. TSA is employed to optimize the parameters of circuit design, like area, power dissipation MOS transistor size, and also used to enhance other circuit specifications, while fulfilling circuit design criteria. The design objectives of CMOS differential amplifier are considered the fitness function of TSA algorithm. Then, weight parameters of CMOS differential amplifier design are optimized using TSA. By CMOS differential amplifier using TSA algorithm, we can optimize circuit design parameters with higher probability of yielding optimal results regarding circuit area lessening, lesser power dissipation and MOS transistor sizes. The proposed method is implemented in the MATLAB platform. The proposed CMOS-DA-TSA method attains 52.01%, 50.29% and 44.30% minimum slew rate, 64.61%, 75.30% and 55.92% minimum power dissipation compared to the existing methods like CMOS-ACD-SOA, CMOS-PAI-FOPSO and CMOS-PSO-MOL, respectively.

This paper investigates the dynamic properties of an inhomogeneous, Bernoulli–Euler multi-segment beam composed of different materials. To the best of knowledge of the authors, the problem of random vibrations of beams composing of different chunks of the beams, namely, strong and weak parts, has not been studied in the literature. In this paper, exact solution of the natural frequencies and associated mode shapes of the multi-segment Bernoulli–Euler beam are obtained using Krylov–Duncan functions, followed by free, forced, and random vibration analyses using the normal mode method. Special emphasis is placed on two special configurations of multi-segment beam, namely, the ‘rigid-soft-rigid beam’ (RSR beam) and ‘soft-rigid-soft beam’ (SRS beam) as simplest manifestations of the multi-chunked structures. Some remarkable properties exhibited by the dynamic response of multi-segment beam are demonstrated through this work, which may be of considerable engineering significance, and could not have been anticipated in advance, especially quantitatively.

This paper presents a detailed study of theoretical performance of graphene field effect transistor (GFET) using analytical approach. GFET shows promising performance in terms of faster saturation as well as extremely high cutoff frequency (3.9THz). A significant shift of the Dirac point as well as an asymmetrical ambipolar behavior is observed on the transfer characteristics. Similarly, an approximate symmetrical capacitance–voltage (C–V) characteristics is obtained where it has guaranteed the consistency because it shows a significant saturation both in the accumulation and inversion region. In addition, a high transconductance of 6800uS at small channel length (20nm) along with high cutoff frequency (3.9THz) has been observed which demands for high speed field effect devices.

This paper presents the analog/RF performance for an III–V semiconductor-based staggered hetero-tunnel-junction n-type nanowire (NW) tunneling field effect transistor (n-TFET), for the first time. The device parameters for analog/mixed-signaling applications, such as transconductance (g_m), transconductance-to-drive current ratio (g_m/I_DS), output resistance (R_out), intrinsic gain and unity-gain cutoff frequency (f_T) are studied for III–V based NW n-TFET, with the help of device simulator and compared with those for a similarly sized homojunction (HJ) NW n-TFET. The result reveals that the hetero-tunnel-junction n-TFETs outperform their HJ counterparts for analog/mixed-signal system-on-chip (SoC) applications.

We report on two-dimensional isothermal simulations of recessed gate and field-plated AlGaN-GaN HFETs with submicron gates. The optimization of the recessed gate shape allows us to reduce the electric field at the drain-side gate edge by approximately 30%. Our simulations reveal a dramatic increase of the effective gate length with increasing drain-to-source bias with a commensurate decrease of the cutoff frequency (up to 40% decrease for 50V). To improve the cutoff frequency for the high drain-to-source bias, we suggest using the second field plate connected to the drain with a small gap between the two field plates. In this design, the electric field in the gap between the gate and the drain field plate is higher leading to a significant reduction of the effective gate length and, as a consequence, to an increase in the cutoff frequency at high drain-to-source biases (compared to the conventional design).

Microwave noise technique is applied to study energy dissipation in an AlN/GaN heterostructure containing a two-dimensional electron gas channel. Measurements of the dissipated power and the noise temperature are performed at 80 K lattice temperature in the electric field range up to 40 kV/cm. The energy relaxation time is found to decrease from 40 ps to 0.55 ps when the bias is increased. The experimental data are discussed in the electron temperature approximation assuming electron energy dissipation on optical phonons and hot-phonon effects. Dependencies of the hot-phonon number and the hot-phonon temperature on the hot-electron temperature are deduced. The frequency cutoff imposed by the limited energy dissipation through optical phonons is estimated.