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64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS

KUO-HSING CHENG

Department of Electrical Engineering, National Central University, Chung-Li, Taoyuan 32001, Taiwan, R.O.C.

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SHUN-WEN CHENG

Department of Electronic Engineering, Far East College, Hsin-Shih, Tainan 74448, Taiwan, R.O.C.

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WEN-SHIUAN LEE

R&D Department, Media Scope Technologies Co., Taipei, Taiwan, R.O.C.

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https://doi.org/10.1142/S0218126606002915Cited by:5 (Source: Crossref)

Abstract

This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

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